Rca Inc.

Thomson, S.a.

Harris Corporation

George R Briggs

Roger Green Stewart

Salomon Vulih

Thomas D Housten

A differential, interpolating, switched capacitor filter and method of operation in which non-interpolating stages of the filter are clocked at a first frequency and a subsequent interpolating stage of the filter is operated at double the first frequency to achieve improved smoothing of the output wave form. The switched capacitors in the interpolating stage which feed forward a differential input from a prior stage to an input to the interpolating stage, and which feed a differential output from the interpolating stage back to an input thereto are paired and switches are provided for the added capacitors so that all of these capacitors are switched. Capacitors which are directly coupled to feed forward a differential input from a prior stage to the interpolating stage are also paired, but only the added capacitor is switched. Other directly coupled capacitors which feed back from the output of the interpolating stage to the input of prior stages are not paired, but are switched to prevent unwanted feedback of the interpolated output to the prior, non-interpolating, stages.

Differential interpolating switched capacitor filter and method

Methods of increasing the number of possible network configurations available during the manufacture of an integrated circuit hybrid balance network containing a fixed number of selectable network configurations in the manufactured network by including a network element selection layer programmable during the manufacturing process. The programming may be accomplished using ROM matrices programmed during or subsequent to the manufacturing process, or alternatively may be accomplished by the programming of the metal masks interconnecting the semiconductor portions of the IC without the necessity for changing the semiconductor masks.

Method of manufacturing a programmable hybrid balance network

A pulse logic circuit comprises a plurality of interconnected stages. Each of the stages includes a relatively large node-charging transistor which, when enabled, forwards charging current to a node from a timing pulse of one of a plurality of phases applied to a load capacitance in series with the node-charging transistor. Such large transistors exhibit significant gate-to-source and gate-to drain distributed capacitances. The response time for charging a selected stage node can be decreased by precharging the gate of the node-charging transistor of a selected stage to enable the transistor prior to the application of a timing pulse, thereby increasing the maximum operating speed of the circuit. Disclosed species of such a pulse logic circuit include time vernier circuits which can be utilized as control circuitry for a liquid crystal television or computer display.

Variable pulse width generator including a timer vernier

A variable width pulse generator includes a plurality of logic stages which are coupled cascade. Each stage is arranged to select one of a plurality of clock signals of differing phase applied thereto responsive to particular bits of a data word defining the pulse width. All of the stages are initially disabled by a precharge pulse occurring at the beginning of each variable pulse interval. The successive stages are enabled by the occurrence of a clock pulse of a clock signal selected by the previous stage. The lastmost stage provides an output corresponding to the width pulse.

Apparatus for generating control pulses of variable width, as for

A variable width pulse generator includes a plurality of logic stages which are coupled in cascade. Each stage is arranged to select one of a plurality of clock signals of differing phase applied thereto responsive to particular bits of a data word defining the pulse width. All of the stages are initially disabled by a precharge pulse occurring at the beginning of each variable pulse interval. The successive stages are enabled by the occurrence of a clock pulse of a clock signal selected by the previous stage. The lastmost stage provides an output corresponding to the variable width pulse.

Circuitry for generating pulses of variable widths from binary input data

A vehicle multiplex system includes a power conductor for conveying electrical power to power-operated units on the vehicle, and a single signal conductor for controlling the connections of power to power-operated units. A multiplex timing unit applys a tri-state timing waveform to the signal conductor. Each of a plurality of control signal transmitters is operative in response to a physical command to apply a corresponding control signal to the signal conductor during a control time period in a channel interval assigned to the particular transmitter. And, each of a plurality of control signal receivers is operative to control the connection of electrical power from the power conductor to a power-operated unit in response to a control signal received from the signal conductor during a control time period in a channel interval assigned to the particulate receiver.

Vehicle multiplex system

A phase locked local oscillator loop of a frequency synthesizer tuning system for a television receiver includes a programmable frequency divider for deriving an output signal having a period which is N times the period of its input signal, N being the number in MHz of the local oscillator frequency required for tuning the receiver to a selected channel (e.g., N = 101 for U.S. channel 2). The 'divide by' number N is controlled by first counting the input signal pulses in groups of (S) pulses, where (S) is a factor equal to the channel separation in MHz (6 in the U.S.). Counting by groups of S continues until the number of such groups equals the channel number, e.g., 2 for channel 2, 83 for channel 83, and then continues for an additional predetermined number of groups of S dependent on the band in which the selected channel resides. The counting then continues in groups of T (T = S-1 is usual) for another predetermined number of groups, likewise dependent on the channel band, until the correct number N of input pulses have been counted, in groups of S and T counts. When the correct N is reached, an output signal is generated and the process is repeated.

Programmable frequency divider for a television receiver frequency

A CMOS shift register cell comprising four transistors and two capacitance elements. Data is temporarily stored in the cell by precharging one capacitance through one of the transistors and then discharging it or not through another of the transistors depending on the input signal level. The second capacitance may be precharged through the third transistor and then discharged or not through the fourth transistor, depending upon the value of the temporarily stored charge.

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Princeton, NJ, United States of America

George R Briggs