Raytheon Company

Lockheed Martin Corporation

George Paloczi

Jeffrey Winfield Scott

John L Vampola

Adam M Kennedy

Christian M Boemler

Micky R Harris

Sean P Kilcoyne

Justin G A Wehner

Neil R Malone

Shelly J Mechery

An apparatus includes a focal plane array configured to receive incoming light. The apparatus also includes a readout integrated circuit configured to generate electrical signals based on the incoming light received by the focal plane array. The apparatus further includes a photonic integrated circuit positioned between the focal plane array and the readout integrated circuit. The photonic integrated circuit is configured to receive the electrical signals and generate output optical signals based on the electrical signals. In some cases, the apparatus may include electrically-conductive vias electrically coupling the focal plane array and the readout integrated circuit, where at least some of the electrically-conductive vias may extend through the photonic integrated circuit. The focal plane array, the readout integrated circuit, and the photonic integrated circuit may form at least part of a monolithic structure.

Integrated photonic integrated circuit (PIC) and readout integrated circuit (ROIC) for high-speed data output from focal plane array

A digital pixel includes a capacitive transimpedance amplifier (CTIA) coupled to a photodiode that receives an electrical charge and output an integration voltage. An integration capacitor coupled to the CTIA accumulates the integration voltage over an integration period. A comparator compares the accumulated integration voltage with a threshold voltage and generates a control signal at a first level each time the accumulated integration voltage is greater than the threshold voltage. A charge subtraction circuit receives the control signal at the first level and discharges the accumulated integration voltage each time the control signal at the first level is received from the comparator. An analog or digital counter receives the control signal at the first level and adjusts a counter value each time the control signal is received from the comparator. An output interface communicates the counter value to an image processing circuit at an end of the integration period.

Digital pixel having high sensitivity and dynamic range

An imaging system includes a focal plane array comprising a first row of photodetectors, a second row of photodetectors adjacent to the first row of photodetectors, and a segmented isolation grid including portions disposed between photodetectors in the first row of photodetectors and photodetectors in the second row of photodetectors.

Segmented channel stop grid for crosstalk mitigation in visible imaging arrays

A strain-balanced photodetector is provided for detecting infrared light at an extended cutoff wavelength in the range of 4.5 &#x3bc;m or more. An InAsSb absorber layer has an Sb content is grown in a lattice-mismatched condition to a GaSb substrate, and a plurality of GaAs strain-compensating layers are interspersed within the absorber layer to balance the strain of the absorber layer due to the lattice mismatch. The strain-compensation layers allow the absorber to achieve a thickness exhibiting sufficient absorption efficiency while extending the cutoff wavelength beyond that possible in a lattice-matched state. Additionally, the strain-compensation layers are sufficiently thin to be substantially quantum-mechanically transparent such that they do not substantially affect the transmission efficiency of the absorber. The photodetector is preferably formed as a majority carrier filter photodetector exhibiting minimal dark current, and may be provided individually or in a focal plane array.

Strain-balanced extended-wavelength barrier detector

Extended wavelength digital alloy NBN detector

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Goleta, CA, United States of America

George Paloczi