Freescale Semiconductor,inc.

Motorola Corporation

Nxp Usa, Inc.

Other

George P Hoekstra

Ravindraraj Ramaraju

Perry H Pelley

Andrew Christopher Russell

Maciej Bajkowski

Prashant U Kenkare

Peter Jeremy Wilson

Troy L Cooper

Lucio F C Pessoa

Jianan Yang

Richard DeWitt Crisp

Hunter Ledbetter Scales, Iii

Thomas W Liston

Lal C Sood

Hamed Ghassemi

Steven C Sullivan

Raymond P Voith

Sujit Sudhaman

Mark W Jetton

Mitchell K Alsup

Eric V Fiene

David P Burgess

Samuel E Alexander

Michael C Shebanow

Jeremiah T Palmer

George G Watkins

Lucio F Pessoa

Perry H Iii Pelley

A method and system are provided for error correction in a memory. Error correction code (ECC) for data stored in a portion of the memory is enabled. A location and number of errors for the portion of the memory is then stored. It is determined if the number of errors exceeds a predetermined number of errors. If the number of errors exceeds the predetermined number, then the data stored in the portion of the memory is refreshed. If refreshing does not correct the errors, then a different ECC may be used.

Memory reliability using error-correcting code

Structures for substituting single bits in an array may include a first array having a plurality of word lines, and for each of the plurality of word lines a memory operable to store a bit substitution column value, and a first data output line operable to communicate the bit substitution column value to a write data shifter. The bit substitution column value may be associated with a bit substitution column in a second array, and the write data shifter may be operable to substitute the bit by shifting data to a redundancy column in the first array.

Memory with redundancy

A method for repairing a memory includes executing an Error Correction Code (ECC) for a page of the memory. The page includes a plurality of bits having an inherent number of failed bits equal to or greater than zero. The ECC is configured to correct a correctable number of failed bits from the plurality of bits. A location of a failure prone bit in the page is determined from a cache in response to the correctable number of failed bits being less than the inherent number of failed bits. A state of the failure prone bit is changed to a new state in response to determining the location of the failure prone bit. The ECC is executed in response to the state of the failure prone bit being changed to the new state.

Error repair location cache

Systems and methods for adaptive error correction codes (ECCs) for electronic memories. In some embodiments, a memory device, may include a first memory having a plurality of address locations, each of the plurality of address locations having a number of storage bits configured to store data and one or more error correction bits corresponding to the data; and a second memory distinct from the first memory, the second memory having a plurality of entries, each of the plurality of entries configured to store one or more operation code bits relating to data stored at a corresponding address location in the first memory, the one or more operation code bits identifying an error correction scheme used to generate the one or more error correction bits at the corresponding address location in the first memory.

Adaptive error correction codes (ECCs) for electronic memories

A memory system includes a memory having a plurality of address locations, each address location configured to store data and one or more error correction bits corresponding to the data. A secondary memory includes a plurality of entries, and each entry configured to store an address value of an address location of the memory and one or more error correction bits corresponding to the data stored at the address location of the memory. The error correction bits in the secondary memory can be used to correct errors in a subset of the memory having a different number of storage bits than the error correction bits in the memory.

Error correction with secondary memory

A method and apparatus are provided for error correction of a memory by using a first memory (), second memory (), and redundant memory () to perform error correction code (ECC) processing on data retrieved from the first memory () by using the redundant memory () to replace entries in the second memory () having repeat addresses, thereby freeing entries in the second memory () for use in detecting and managing errors identified by the ECC processing.

Memory redundancy to replace addresses with multiple errors

A memory system includes a memory and a content addressable memory (CAM). The memory includes a plurality of address locations, wherein each address location configured to store data and one or more error correction bits corresponding to the data. The CAM includes a plurality of entries, wherein each entry configured to store an address value of an address location of the memory and one or more extended error correction bits corresponding to the data stored at the address location of the memory.

Error correction with extended CAM

In accordance with at least one embodiment, column level power control granularity is provided to control a low power state of a memory using a drowsy column control bit to control the low power state at an individual column level to protect the memory from weak bit failure. In accordance with at least one embodiment, a method of using a dedicated row of bit cells in a memory array is provided wherein each bit in the row controls the low power state of a respective column in the array. A special control signal is used to access the word line, and the word line is outside of the regular word line address space. A mechanism is provided to designate the weak bit column and set the control bit corresponding to that particular column to disable the drowsy/low power state for that column.

Memory column drowsy control

A memory having a memory array having a plurality of word lines, a plurality of bit cells coupled to the word lines, and a plurality of control memory cells coupled to the word lines. Each word line of the plurality of word lines has a control memory cell coupled thereto and each control memory cell has an output. The memory also has a plurality of logic circuits coupled to the plurality of word lines. The output of each control memory cell is coupled to a corresponding one of the plurality of logic circuits. The plurality of logic circuits prevents access to the word line selected by a row address if the output of the control memory cell coupled to the selected word line is in a first logic state.

Memory with word line access control

A circuit for determining a threshold indication of temperature with respect to a threshold temperature. The circuit includes a timer circuit and a temperature sensor circuit having an counter whose output has a relationship to temperature. At the end of a period determined by the timer circuit, a comparator circuit compares the count of the counter with an indication of the threshold temperature to determine a state of the threshold indication. In response to a change in state of the threshold indication, the circuit changes one of the count time or the counter output's relationship to temperature to provide a hysteresis for the threshold indication.

Temperature threshold circuit with hysteresis

A method and apparatus are provided for error correction of a memory by using a first memory () and second memory () to perform error correction code (ECC) processing on data retrieved from the first memory and to use status control bits (-) in the second memory to detect and manage hard and soft errors identified by the ECC processing.

Memory ECC with hard and soft error detection and management

A memory device includes a plurality of sense amplifiers, an array of memory cells including a first subset of memory cells, and a plurality of word lines. Each word line is coupled to each memory cell in a respective row of the memory cells and each row of the memory cells includes one memory cell of the first subset of memory cells. Each of a plurality of control word lines is coupled to a respective one of the memory cells in the first subset of memory cells and each of the memory cells in the first subset of memory cells generates a sense amplifier control signal coupled to control operation of a respective one of the plurality of sense amplifiers.

Memory with power savings for unnecessary reads

A dynamic logic circuit includes an N channel transistor stack between a dynamic node and a first power supply terminal for receiving a plurality of logic signals. A P channel clock transistor is coupled between a second power supply terminal and the dynamic node is for receiving a clock signal. An N channel clock transistor is in series with the N channel stack and is between the dynamic node and the first power supply terminal is for receiving the clock signal. A keeper transistor has a first current electrode coupled to the dynamic node, a second current electrode coupled to a second power supply terminal, and a control electrode. A static logic circuit has an output for providing an output responsive to a state of the logic signals. The output is coupled to the control electrode of the keeper transistor.

Dynamic logic circuit

A dynamic logic circuit includes an N channel transistor stack between a dynamic node and a first power terminal for receiving a plurality of logic signals. A first clock transistor is coupled between a second power terminal and the dynamic node for receiving a clock signal. A second clock transistor is in series with the N channel stack, between the dynamic node and a second power terminal, and for receiving the clock signal. An inverter circuit has an input coupled to the dynamic node and an output. A keeper transistor has a control electrode coupled to the output of the inverter circuit, a first current electrode coupled to the dynamic node, and a second current electrode. A plurality of P channel transistors, which are coupled in parallel, are coupled between the keeper transistor and the second power terminal and are for receiving the plurality of logic signals.

A method for refreshing a Dynamic Random Access Memory (DRAM) includes performing a refresh on at least a portion of the DRAM at a first refresh rate, and performing a refresh on a second portion of the DRAM at a second refresh rate. The second portion includes one or more rows of the DRAM which do not meet a data retention criteria at the first refresh rate, and the second refresh rate is greater than the first refresh rate.

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Austin, TX, United States of America

George P Hoekstra