Matsushita Electric Industrial Co., Ltd.

Panasonic Corporation

Matsushita Electronics Corporation

George Nakane

Tatsumi Sumi

Hiroshige Hirano

Nobuyuki Moriwaki

Tetsuji Nakakuma

Toshio Mukunoki

Yoshitaka Mano

Toshiyuki Honda

Kazuki Yoshioka

Mitsuyoshi Ohya

The present invention extends the reading range between a contactless type information medium (semiconductor integrated circuit) and a reader/writer, which exchanges data in contactless communications with the contactless type information medium, and enables a stable data exchange even if the power supply voltage is lowered when data is returned from the contactless type information medium to the reader/writer. Specifically, when data is returned from the contactless type information medium, the data to be returned is held in the logic circuit sectioncapable of operating at a lower voltage than the non-volatile memory circuit section, and the reset detection lower limit voltage to be used by the reset generating circuitduring the data-returning period is set to be lower than that during periods other than the data-returning period.

Semiconductor integrated circuit and noncontact information system including it

A semiconductor device according to the present invention comprises a first non-volatile memory, a second non-volatile memory in which initial data is stored, and an initialization controller for initializing the first non-volatile memory, wherein the second non-volatile memory has anti-stress properties higher than those of the first non-volatile memory, and the initialization controller reads the initial data from the second non-volatile memory when the first non-volatile memory is initialized and copies the read initial data in the first non-volatile memory to thereby initialize the first non-volatile memory.

Semiconductor device and IC card

A semiconductor integrated circuit includes a supply voltage generator for rectifying a signal received by an antenna coil and generating a supply voltage set at a predetermined voltage by a regulator, and a demodulator. The demodulator includes a demodulation circuit for demodulating an input signal and outputting the demodulated input signal, a resistor whose one end is connected to one end of the antenna coil, a diode whose anode is connected to the other end of the resistor and whose cathode is connected to a node located to the input end of the demodulation circuit, a first capacitance connected between a node at which the resistor and the diode are connected to each other and a grounding conductor, and a second capacitance connected between a node at which the diode and the demodulation circuit are connected to each other and a grounding conductor.

Semiconductor integrated circuit and noncontact information medium

A semiconductor memory device includes a voltage reduction circuit which reduces a power supply voltage and outputs an internal voltage, a nonvolatile memory connected to the internal voltage and a current consumption control circuit including a switch transistor and a resistor. In this case, the amount of electric current which the nonvolatile memory consumes and the amount of electric current which the resistor consumes are substantially the same. When the nonvolatile memory is in a non-operation state, the current consumption control circuit turns ON the switch transistor by a memory activation signal and consumes substantially the same amount of electric current as the amount of electric current which the nonvolatile memory consumes. When the nonvolatile memory is in an operation state, the current consumption control circuit turns OFF the switch transistor and stops electric current consumption by the resistor.

Current switching for maintaining a constant internal voltage

A semiconductor integrated circuit is provided to allow a stable operation even in a short distance where an IC card is in contact with a reader/writer. In a semiconductor integrated circuit for a noncontact IC card that obtains driving power supply by carrying superimposed data, obtained voltage does not become overvoltage and data can be demodulated with stability regardless of a change in communication distance. Inputs of a system (including a rectifier circuit and a power supply circuit) producing power supply from an antenna coil of the IC card which receives radio waves transmitted from a reader/writer, and of a demodulator circuit are connected via a path separated from the output of the rectifier circuit. Thus, a power supply voltage range can be set within a permissible value and a rate of change in input of the demodulator circuit can be obtained regardless whether the communication distance is short or long.

Semiconductor integrated circuit

A semiconductor device includes a plurality of semiconductor integrated circuits formed on a semiconductor wafer; an testing pad for inputting and outputting a signal to and from an internal circuit of the semiconductor integrated circuit; a switch for switching a state of a connection between the semiconductor integrated circuit and the testing pad; and a wiring pattern formed on a parting line around the semiconductor integrated circuit and connected to an input terminal of the switch. When the semiconductor integrated circuits are separated, cutting off of the wiring pattern causes the switch to be turned off, so that the internal circuit is prevented from being affected by the influence of the cutting plane.

Semiconductor device

A reference potential generator is constituted of two signal lines 21 and 22; a charge supplier to supply charge to signal lines 21 and 22; connectors 24a and 24b connecting the charge supplier 23 and two signal lines 21 and 22 in order to supply charge to the two signal lines; and a connector 25 connecting two signal lines 21 and 22 together by the second control signal, and two signal lines are disconnected after the potentials of the two signal lines determined by the supplied charge and each of load capacitances of signal lines are averaged. A semiconductor memory device of the invention incorporating the above reference potential generator generating an exact reference potential, is able to amplify and output the potential difference between the reference potential and the potential of data readout in the bit line, and by this, '1' or '0' of readout data can be precisely determined.

Reference potential generator and a semiconductor memory device having

A reference potential generator is constituted of two signal lines 21 and 22; a charge supplying circuit to supply charge to signal lines 21 and 22; a first connection circiut 24a and 24b connecting the charge supplying circuit 23 and two signal lines 21 and 22 in order to supply charge to the two signal lines; and a second connection circuit 25 connecting two signal lines 21 and 22 together by the second control signal, and two signal lines are disconnected after the potentials of the two signal lines determined by the supplied charge and each of load capacitances of signal lines are averaged. A semiconductor memory device of the invention incorporating the above reference potential generator generating an exact reference potential, is able to amplify and output the potential difference between the reference potential and the potential of data readout in the bit line, and by this, '1' or '0' of readout data can be precisely determined.

A reference potential generator is constituted of two signal lines 21 and 22; a charge supplying means to supply charge to signal lines 21 and 22; a first connection circuit 24a and 24b connecting the charge supplying circuit 23 and two signal lines 21 and 22 in order to supply charge to the two signal lines; and a second connection circuit 25 connecting two signal lines 21 and 22 together by the second control signal, and two signal lines are disconnected after the potentials of the two signal lines determined by the supplied charge and each of load capacitances of signal lines are averaged. A semiconductor memory device of the invention incorporating the above reference potential generator generating an exact reference potential, is able to amplify and output the potential difference between the reference potential and the potential of data readout in the bit line, and by this, '1' or '0' of readout data can be precisely determined.

A memory cell comprises a ferroelectric capacitor, first main memory cells are connected to a first bit line, a first reference memory cell is connected to a second bit line, second main memory cells are connected to the second bit line, and a second reference memory cell is connected to the first bit line. When a first operation mode is selected by a control circuit comprising NAND gates and NOR gates, first main memory cells and first reference memory cell are selected, and when a second operation mode is selected, first main memory cells and second main memory cells are selected. Thus, by switching the operation between the two operation modes, a ferroelectric memory device that has stable operation at a low voltage and high integration at a high voltage is provided.

Ferroelectric memory devices and method for testing them

The life of a semiconductor memory device can be prolonged by using a plurality of memory cells and decreasing the stress applied to the dielectric film of the memory cells storing a data value '1.' This is achieved in the present invention by decreasing the number of rewritings required to retain stored data. Specifically, the present invention utilizes a reverse and rewrite means to reverse and rewrite data back into memory cells after being read, memory means for memorizing a signal indicating whether the currently stored data is in a reversed state, and judging means for judging whether the data should be reversely output.

Semiconductor memory device including reverse and rewrite means

A semiconductor memory device comprises a main memory cell, a redundant memory cell, a redundant address data cell comprising a non-volatile memory which electrically memorizes an address of a redundant memory cell which replaced a failed memory cell in the main memory cell, a control circuit 15 and a redundant memory cell selecting circuit 16. The redundant memory cell selecting circuit serves to hold first address data which has been read from the redundant address data cell, and to compare the first address data with second address data for a read or write operation which is input via the control circuit and thereby select the main memory cell or the redundant memory cell.

Semiconductor memory device with redundant memory cell backup

A semiconductor memory device comprising a pair of bit lines, a word line, a cell plate electrode, a memory cell connected to each of the bit lines, the word line and the cell plate electrode, and a prevention means that permits only a predetermined number of readouts of data stored in the memory cell, after which the data is destroyed and is not retrieved with subsequent readout attempts.

Semiconductor memory device

Bit lines BL0 and /BL0 are connected to a sense amplifier SA0, the gate of a first MOS transistor to a first word line WL0, a first electrode of a first ferrodielectric capacitor Cs1 to the source of the first Qn, the drain of the first Qn to BL0, a second electrode of Cs1 to a first plate electrode CP0, the gate of a second MOS transistor Qn to a second word line DWL0, a first electrode of a second ferrodielectric capacitor Cd2 to the source of the second Qn, the drain of the second Qn to /BL0, and a second electrode of Cd1 to a second plate electrode DCP0, and after turning off the second Qn, the logic voltage of DCP0 is inverted. Hence, in a semiconductor memory device employing the ferrodielectric element, the dummy memory capacitor is initialized securely, and high speed reading is enabled without concentration of power consumption.

Bit lines BL0 and /BL0 are connected to a sense amplifier SA0, the gate of a first MOS transistor to a first word line WL0, a first electrode of a first Ferroelectric capacitor Cs1 to the source of the first Qn, the drain of the first Qn to BL0, a second electrode of Cs1 to a first plate electrode CP0, the gate of a second MOS transistor Qn to a second word line DWL0, a first electrode of a second Ferroelectric capacitor Cd2 to the source of the second Qn, the drain of the second Qn to /BL0, and a second electrode of Cd1 to a second plate electrode DCP0, and after turning off the second Qn, the logic voltage of DCP0 is inverted. Hence, in a semiconductor memory device employing the Ferroelectric element, the dummy memory capacitor is initialized securely, and high speed reading is enabled without concentration of power consumption.

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Nara, Japan

George Nakane