Intel Corporation

Virident Systems, Inc.

Western Digital Technologies, Inc.

George Moussa

Kumar Ganapathy

Kenneth Alan Okin

Saurin Shah

Ruban Kanapathippillai

Earle F Philhower, Iii

Ruchir Shah

Vijay Karamcheti

Rajesh Parekh

Ashish Singhai

Sandeep Sharma

Krishanth Skandakumaran

Rajendra Prasad Mishra

Sriram Rupanagunta

Srikant Sadasivam

Embodiments of the present invention receive I/O commands expressed in either vendor-specific or non-vendor-specific protocols and normalize them into a common format for execution by different memory devices. Embodiments of the present invention identify these I/O commands using parameters common to both types of protocols. In this fashion, embodiments store normalized commands in data structures for execution by memory devices in which the normalized commands represent instructions for performing an action corresponding with execution of the original I/O command. Accordingly, embodiments of the present invention save resources with respect to hardware and software maintenance costs.

Method and system for a common processing framework for memory device controllers

Embodiments of the present invention are operable to efficiently schedule memory device commands, such as flash memory device commands, while taking into account the interdependencies of processing such commands. As such embodiments of the present invention order commands to make sure that data is written and read from memory devices in a coherent fashion using command groups. Commands within such command groups are scheduled concurrently or in parallel. In this fashion, embodiments of the present invention promote efficient execution of memory device commands while maintaining any required arbitrary ordering requirements.

Method and system for efficient common processing in memory device controllers

A computer system is disclosed including a printed circuit board (PCB) including a plurality of traces, at least one processor mounted to the PCB to couple to some of the plurality of traces, a heterogeneous memory channel including a plurality of sockets coupled to a memory channel bus of the PCB, and a memory controller coupled between the at least one processor and the heterogeneous memory channel. The heterogeneous memory channel includes a plurality of sockets coupled to a memory channel bus of the PCB. The plurality of sockets are configured to receive a plurality of different types of memory modules. The memory controller may be a programmable heterogeneous memory controller to flexibly adapt to the memory channel bus to control access to each of the different types of memory modules in the heterogeneous memory channel.

Methods of communicating to different types of memory modules in a memory channel

A translating memory module is disclosed including a printed circuit board, at least one memory integrated circuit coupled to the printed board, and at least one support chip coupled to the printed circuit board and coupled between the edge connector and the at least one memory integrated circuit. The at least one support chip includes a bi-directional translator to translate between a first memory communication protocol for the at least one memory integrated circuit and a second memory communication protocol for a memory channel differing from the first memory communication protocol. The second memory communication protocol to communicate data, address, and control signals over the memory channel bus to read and write data into the memory of the translating memory module.

Systems with programmable heterogeneous memory controllers for main memory

A distributed direct memory access (DMA) method, apparatus, and system is provided within a system on chip (SOC). DMA controller units are distributed to various functional modules desiring direct memory access. The functional modules interface to a systems bus over which the direct memory access occurs. A global buffer memory, to which the direct memory access is desired, is coupled to the system bus. Bus arbitrators are utilized to arbitrate which functional modules have access to the system bus to perform the direct memory access. Once a functional module is selected by the bus arbitrator to have access to the system bus, it can establish a DMA routine with the global buffer memory.

Method and apparatus for distributed direct memory access for systems on chip

Translating memory modules for main memory

Programmable heterogeneous memory controllers for main memory with different memory modules

Systems and apparatus with programmable memory control for heterogeneous main memory

Distributed direct memory access for systems on chip

A direct memory access (DMA) descriptor table to control DMA of information in a memory is disclosed. The DMA descriptor table includes one or more DMA descriptor lists stored in the memory. Each DMA descriptor lists may include one or more pointers and information regarding the type of data being directly memory accessed. The pointers may point to a starting address in the memory from which to directly memory access data, prior state information, or program code from and to the memory.

Tables with direct memory access descriptor lists for distributed direct memory access

Growing community of inventors

Dublin, CA, United States of America

George Moussa