Vanguard International Semiconductor Corporation

Vanguard International Semiconductor Manufacturing

George Meng-Jaw Cherng

Min-hwa Chi

A twin bit DRAM cell capable of storing two bits of digital data as stored charge within the DRAM cell is disclosed. The twin bit DRAM cell has two pass transistors, a trench capacitor, and a stack capacitor. The pass transistors each have a source connected to a bit line voltage generator to control placement of the charge within the twin bit DRAM cell, a gate connected to a word line voltage generator to control activation of the DRAM cells, and a drain. The trench capacitor has a top plate connected to the drain of the first pass transistor and a bottom plate connected to a first biasing voltage source. The stack capacitor has a first plate connected to the drain of the second pass transistor and a second plate connected to a second biasing voltage generator. Twin bit DRAM cells will be arranged in a plurality of rows and columns to form an array of twin bit DRAM cells.

DRAM cell and array to store two-bit data having merged stack capacitor and trench capacitor

A new and improved method for fabricating planarized isolation trenches, wherein erosion of insulating material at the edges of trenches is surpressed without sacrificing a minimal width of the isolation trench, has been developed. The process fabricates sidewall spacers before etching the isolation trench into the semiconductor substrate. After filling the etched trench with insulating material and plartarization of the insulating material, the sidewall spacers protect the insulating material filling the trench and prevent the formation of 'divots' at the edges of the trench. Since the spacers are formed prior to the etching of the trench in the semiconductor substrate, a minimal width of the isolation trench can be maintained and less area is required for the isolation trench.

Method of forming shallow trench isolation for integrated circuit

A method for making a planarized capacitor-over-bit lines structure on dynamic random access memory devices was achieved. After forming the array of FETs for the memory cells, a first polysilicon layer is deposited and patterned to simultaneously form bit lines and polysilicon landing pads that also form the node contacts for stacked capacitors. A thick first insulating layer is deposited and planarized. Node contact openings are etched in the first insulating layer to the landing pads and a thin second polysilicon layer is deposited which also fills the contact openings. Trenches are etched through the second polysilicon layer and into the first insulating layer around the desired capacitor areas while protecting the remaining DRAM chip area from etching. A thin third polysilicon layer is deposited and etched back to form sidewall spacers and to form capacitor bottom electrodes with increased capacitance. A thin interelectrode dielectric layer is deposited followed by a relatively thin fourth polysilicon layer. A photoresist mask is used to pattern the thin fourth polysilicon to form the capacitor plate electrode and to concurrently etch the thin second polysilicon to the planar first insulating layer providing an array of memory cells that are essentially planar with the peripheral areas of the DRAM chip areas.

Method for making a planarized capacitor-over-bit-line structure for

Dram cell and array to store two-bit data having merged stack capacitor

A method is described for forming capacitor plates with extended surface area using polysilicon hemispherical grains or HSG polysilicon. The HSG polysilicon is formed on the top surface and sidewalls of first capacitor plates. A vertical anisotropic etching step forms an irregular top surface of the first capacitor plates and an anneal step provides good adhesion between the grains of HSG polysilicon and the sidewalls of the first capacitor plates. A timed etchback of the dielectric between the first capacitor plates insures good electrical insulation between adjacent first capacitor plates.

Method to improve yield for capacitors formed using etchback of

A method for making memory cells having self-aligned node contacts to bit lines was achieved. After forming the array of FETs for the memory cells, a first insulating layer is deposited and planarized. A single masking step is used to concurrently etch bit lines and node contact openings for crown capacitors. A second polysilicon layer and a silicide layer are deposited to form a polycide layer which is specially patterned to form bit lines with portions of the polycide layer extending over the node contacts. A second insulating layer (e.g., BPSG) is deposited and openings are etched aligned over the node contacts to the polycide. The polycide is selectively etched in the openings to electrically isolate the individual bit lines and concurrently form self-aligned node contacts. A third insulating layer is deposited and etched back to form insulating sidewall liners on the bit lines. A third polysilicon layer is deposited and polished back to form an array of bottom electrodes in the openings for crown capacitors. An interdielectric layer and a fourth polysilicon layer are deposited, and the fourth polysilicon layer is patterned to complete the array of crown capacitors for the DRAM device.

Growing community of inventors

Hsinchu, Taiwan

George Meng-Jaw Cherng