Intel Corporation

George Matthew

Harish Krishnamurthy

Krishnan Ravichandran

Vaibhav Vaidya

Pavan Kumar

Wayne Proefrock

Rinkle Jain

Sheldon Weng

Gerhard Schrom

Willem M Beltman

Anant S Deval

Alexander Lyakhov

Ramnarayanan Ram Muthukaruppan

Mark L Neidengard

Jessica Gullbrand

Annabelle Pratt

Tarun Mahajan

Sergio Carlo Rodriguez

Bharani Thiruvengadam

Karthik Sankaranarayanan

Rachid Rayess

Srinivasulu Malepati

Pushkar Dixit

James Alexander Darnes

Described is an apparatus which comprises: an output node; a capacitor; an inductor having a first terminal coupled to the output node, and a second terminal coupled to the capacitor; a bridge to receive an input power supply and to generate a switching voltage signal at the output node; and a current sensor to determine slope of the switching voltage signal on the output node.

Digital current sensor for on-die switching voltage regulator

An apparatus is provided which comprises: at least two switches in series between an input voltage node and a ground terminal; an inductor coupled between a mid-point of the at least two switches and an output terminal; a first circuitry to compare a current through the inductor with a threshold current, and to control one or both of the at least two switches, based at least in part on the comparison; and a second circuitry to randomly vary the threshold current over consecutive cycles of switching of the at least two switches.

Reducing electromagnetic interference in switching regulators

Methods and apparatus relating to a low ripple mechanism of mode change in switched capacitor voltage regulators are described. In an embodiment, a mode change of a Switching Capacitor Voltage Regulator (SCVR) is caused based at least in part on a comparison of an output voltage of the SCVR and a reference voltage. The output voltage is sensed based at least in part on a clock signal. Other embodiments are also disclosed and claimed.

Low ripple mechanism of mode change in switched capacitor voltage regulators

Methods and apparatus relating to low cost and/or low overhead serial interface for power management and other IC (Integrated Circuit) devices are described. In an embodiment, a unique address is assigned to each of a plurality of slave devices. The plurality of slave devices are coupled in a daisy chain configuration. And, any access directed at a first slave device from the plurality of slave devices is allowed based at least in part on comparison of an address of the first slave device and an address associated with the access. Other embodiments are also disclosed and claimed.

Low cost low overhead serial interface for power management and other ICs

Methods and apparatus relating to reducing switching noise and improving transient response in voltage regulators are described. In an embodiment, one or more pulses are inserted into an output waveform of a voltage regulator. The one or more pulses introduce multiple frequencies into the output waveform of the voltage regulator (e.g., to reduce acoustic noise). In another embodiment, the output voltage of a voltage regulator is modified in response to comparison of the output voltage with at least one of a plurality of threshold values. The plurality of threshold values includes an upper trigger point voltage value and a lower trigger point voltage value. Other embodiments are also disclosed and claimed.

Techniques for reducing switching noise and improving transient response in voltage regulators

Pulse width modulation (PWM) based on selectable phases of a system clock may be implemented with respect to leading-edge-modulation (LEM), trailing-edge-modulation (TEM), and/or dual-edge-modulation. An initial pulse may be generated based on a duty command, synchronous with the system clock, and may be registered with a D flip-flop under control of a selected phase of the system clock. Alternatively, a target count may be derived from the duty command, and an edge of the PWM pulse may be initiated when a count of the selected phase equals the target count. The pulse edge may be registered by a D flip-flop to a SR flip-flop under control of the selected phase. The phases of the system clock may be shared amongst multiple systems to generate multiple PWM signals. A system may include a DLL and digital logic, which may consist essentially of combinational logic and registers.

Hybrid digital pulse width modulation (PWM) based on phases of a system clock

Described is a pulse width modulation architecture for high speed digitally controlled voltage regulator. Described is an apparatus which comprises: a first phase interpolator (PI) for coupling an input to a delay element of a delay line, wherein the coupling is via a selection unit; a second PI for coupling an output of the delay element of the delay line, wherein the coupling is via the selection unit; and a third PI for providing an output, the third PI calibrated according to delay settings of the first and second PIs.

Pulse width modulator for high speed digitally controlled voltage regulator

Growing community of inventors

Hillsboro, OR, United States of America

George Matthew