Sandisk Technologies Inc.

Sandisk Corporation

Micron Technology Incorporated

Sandisk 3d LLC

Lam Research Corporation

George Matamis

James K Kai

Vinod Robert Purayath

Henry Chien

Takashi Whitney Orimoto

Raghuveer S Makala

Rahul Sharangpani

Tuan Duc Pham

Yao-Sheng Lee

Johann Alsmeier

Senaka Kanakamedala

Masaaki Higashitani

Yanli Zhang

Jayavel Pachamuthu

Henry Chin

Jeffrey W Lutze

George Samachisa

Yingda Dong

Nima Mokhlesi

Hiroyuki Kinoshita

Wei Zhao

Yupin K Fong

Nancy M Lomeli

Dana Lee

Chang Hua Siau

Paolo Tessariol

Chet E Carter

Kunal R Parekh

Eli Harari

Roy E Scheuerlein

John David Hopkins

Er-Xuan Ping

Hiroyuki Ogawa

Eric A Hudson

Ching-Huang Lu

Lifang Xu

Graham Richard Wolstenholme

Raashina Humayun

Hao Fang

Jian Li

Anilkumar Chandolu

Patrick A Van Cleemput

Samantha SiamHwa Tan

Masanori Tsutsumi

Shih-Ked Lee

Steven J Radigan

Chun-Ming Wang

Yang Pan

Juwen Gao

Andrew C Lin

Albert Fayrushin

Jixin Yu

Yuan Zhang

Sateesh Koka

Donovan Lee

Thomas Jongwan Kwon

Zhenyu Lu

Somesh Peri

Yifen Liu

Hidetaka Horiuchi

Naoki Takeguchi

Erik R Byers

Daxin Mao

Genta Mizuno

Justin D Shepherdson

Tecla Ghilardi

Junichi Ariyoshi

Wenguang Shi

Kalyan Chakravarthy Kavalipurapu

Jarrett Jun Liang

Seiji Shimabukuro

Christopher J Larsen

Helen H Zhu

Akhil N Singhal

Yongsik Yu

Damir Fazil

Joydeep Guha

Vinayak Shamanna

Prakash Rau Mokhna Rau

Dengliang Yang

M Jared Barclay

Joon Hong Park

S M Istiaque Hossain

Merri Lyn Carlson

Chun Ge

Nikhil Dole

Tomohiro Kubo

Shigehiro Fujino

Saurabh Keshav

Arun Kumar Dhayalan

Jiyin Xu

Xiaolong Hu

Chen-Che Huang

Karthik Subramanian Colinjivadi

Koji Miyata

Joel D Peterson

Naiming Liu

Stephen Shi

Young Joon Moon

Rokibul Islam

An electronic device comprises a stack of alternating dielectric materials and conductive materials, a pillar region extending vertically through the stack, an oxide material within the pillar region and laterally adjacent to the dielectric materials and the conductive materials of the stack, and a storage node laterally adjacent to the oxide material and within the pillar region. A charge confinement region of the storage node is in horizontal alignment with the conductive materials of the stack. A height of the charge confinement region in a vertical direction is less than a height of a respective, laterally adjacent conductive material of the stack in the vertical direction. Related methods and systems are also disclosed.

Electronic devices comprising reduced charge confinement regions in storage nodes of pillars and related methods

A memory device includes a memory array of memory cells and control logic, operatively coupled with the memory array. The control logic is to perform operations, which include causing the memory cells to be programmed with an initial voltage distribution representing multiple logical states; causing the memory cells to be programmed with a subsequent voltage distribution representing a subset of the multiple logical states at a higher voltage than that of the initial voltage distribution, wherein the subset of the multiple logical states is compacted above a program verify voltage level for the subsequent voltage distribution; and causing a first program verify operation of the subsequent voltage distribution to be performed on the memory cells to verify one or more voltage levels of the subsequent voltage distribution.

Distributed compaction of logical states to reduce program time

A microelectronic device comprises a first set of tiers, each tier of the first set of tiers comprising alternating levels of a conductive material and an insulative material and having a first tier pitch, a second set of tiers adjacent to the first set of tiers, each tier of the second set of tiers comprising alternating levels of the conductive material and the insulative material and having a second tier pitch less than the first tier pitch, a third set of tiers adjacent to the second set of tiers, each tier of the third set of tiers comprising alternating levels of the conductive material and the insulative material and having a third tier pitch less than the second tier pitch, and a string of memory cells extending through the first set of tiers, the second set of tiers, and the third set of tiers. Related microelectronic devices, electronic systems, and methods are also described.

Microelectronic devices including varying tier pitch, and related electronic systems

Various embodiments herein relate to methods, apparatus, and systems for etching a feature in a substrate. Typically the feature is etched in a dielectric-containing stack. The etching process involves cyclically etching the feature and depositing a protective film on sidewalls of the partially etched feature. These stages are repeated until the feature reaches its final depth. The protective film may have a particular composition, for example including at least one of a tungsten carbonitride, a tungsten sulfide, tin, a tin-containing compound, molybdenum, a molybdenum-containing compound, a ruthenium carbonitride, a ruthenium sulfide, an aluminum carbonitride, an aluminum sulfide, zirconium, and a zirconium-containing compound. A number of optional steps may be taken including, for example, doping the mask layer, pre-treating the substrate prior to deposition, removing the protective film from the sidewalls, and oxidizing any remaining protective film.

Metal-containing passivation for high aspect ratio etch

Some embodiments include an assembly having a memory stack which includes dielectric levels and conductive levels. A select gate structure is over the memory stack. A trench extends through the select gate structure. The trench has a first side and an opposing second side, along a cross-section. The trench splits the select gate structure into a first select gate configuration and a second select gate configuration. A void is within the trench and is laterally between the first and second select gate configurations. Channel material pillars extend through the memory stack. Memory cells are along the channel material pillars.

Assemblies comprising memory cells and select gates

Some embodiments include an integrated assembly having a first deck. The first deck has first memory cell levels alternating with first insulative levels. A second deck is over the first deck. The second deck has second memory cell levels alternating with second insulative levels. A cell-material-pillar passes through the first and second decks. Memory cells are along the first and second memory cell levels and include regions of the cell-material-pillar. An intermediate level is between the first and second decks. The intermediate level includes a buffer region adjacent the cell-material-pillar. The buffer region includes a composition different from the first and second insulative materials, and different from the first and second conductive regions. Some embodiments include methods of forming integrated assemblies.

Integrated assemblies, and methods of forming integrated assemblies

Microelectronic devices include stadium structures within a stack structure and substantially symmetrically distributed between a first pillar structure and a second pillar structure, each of which vertically extends through the stack structure. The stack structure includes a vertically alternating sequence of insulative materials and conductive materials arranged in tiers. Each of the stadium structures includes staircase structures having steps including lateral ends of some of the tiers. The substantially symmetrical distribution of the stadium structures, and fill material adjacent such structures, may substantially balance material stresses to avoid or minimize bending of the adjacent pillars. Related methods and systems are also disclosed.

Microelectronic devices with symmetrically distributed staircase stadiums and related systems and methods

A method used in forming a memory array comprising strings of memory cells comprises forming a construction comprising a stack that have vertically-alternating insulative tiers and wordline tiers. An array of openings is formed in an uppermost portion of upper material that is above the stack, and the openings comprise channel openings and dummy openings. At least the uppermost portion of the upper material is used as a mask while etching the channel openings and the dummy openings into a lower portion of the upper material. The channel openings are etched into the insulative and wordline tiers. The channel openings are etched deeper into the construction than the dummy openings, and channel material is formed in the channel openings after the etching. Structures independent of method are disclosed.

Methods used in forming a memory array comprising strings of memory cells

Microelectronic devices including a varying tier pitch, and related electronic systems and methods

Methods, apparatus and systems for forming a recessed feature in dielectric material on a semiconductor substrate are provided. Separate etching and deposition operations are employed in a cyclic manner. Each etching operation partially etches the feature. Each deposition operation forms a protective film on the sidewalls of the feature to prevent lateral etch of the dielectric material during the etching operations. The protective film may be deposited under different conditions (e.g., pressure, duration of reactant delivery, duration of plasma exposure, RF power, and/or RF duty cycle, etc.) in different deposition operations. Such conditions may affect the degree of conformality at which the protective film forms. In various embodiments, one or more protective films may be sub-conformal. In these or other embodiments, one or more other protective films may be conformal.

Technique to tune sidewall passivation deposition conformality for high aspect ratio cylinder etch

A memory film and a semiconductor channel can be formed within each memory opening that extends through a stack including an alternating plurality of insulator layers and sacrificial material layers. After formation of backside recesses through removal of the sacrificial material layers selective to the insulator layers, a metallic barrier material portion can be formed in each backside recess. A cobalt portion can be formed in each backside recess. Each backside recess can be filled with a cobalt portion alone, or can be filled with a combination of a cobalt portion and a metallic material portion including a material other than cobalt.

Cobalt-containing conductive layers for control gate electrodes in a memory structure

A method for selectively etching a tungsten layer on a substrate includes arranging a substrate including a tungsten layer on a substrate support. The substrate processing chamber includes an upper chamber region, an inductive coil arranged outside of the upper chamber region, a lower chamber region including the substrate support and a gas dispersion device arranged between the upper and lower chamber regions. The gas dispersion device includes a plurality of holes in fluid communication with the upper and lower chamber regions. The method further includes controlling pressure in the substrate processing chamber in a range from 0.4 Torr to 10 Torr; supplying an etch gas mixture including fluorine-based gas to the upper chamber region; striking inductively coupled plasma in the upper chamber region by supplying power to the inductive coil; and selectively etching the tungsten layer relative to at least one other film material of the substrate.

Systems and methods for selectively etching tungsten in a downstream reactor

A method of making a monolithic three dimensional NAND string which contains a semiconductor channel and a plurality of control gate electrodes, includes selectively forming a plurality of discrete charge storage regions using atomic layer deposition. The plurality of discrete charge storage regions includes at least one of a metal or an electrically conductive metal oxide.

Vertical floating gate NAND with selectively deposited ALD metal films

A memory film and a semiconductor channel can be formed within each memory opening that extends through a stack including an alternating plurality of insulator layers and sacrificial material layers. After formation of backside recesses through removal of the sacrificial material layers selective to the insulator layers, a metallic barrier material portion can be formed in each backside recess. A molybdenum-containing portion can be formed in each backside recess. Each backside recess can be filled with a molybdenum-containing portion alone, or can be filled with a combination of a molybdenum-containing portion and a metallic material portion including a material other than molybdenum.

Molybdenum-containing conductive layers for control gate electrodes in a memory structure

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San Jose, CA, United States of America

George Matamis