Burroughs, Inc.

Advanced Micro Devices Corporation

Bell Telephone Laboratories

George Marr

Patrick T Chuang

George Elwood Smith

A plurality of capacitive memory elements are coupled between two pairs of bit line and return line halves. A cross-coupled MOSFET sense amplifier, configured to operate in a race mode, connects between the two bit line/return line pairs. The return line of each bit line/return line pair is coupled to the bit line of the other pair so that when any selected memory element is read to generate a data signal on the bit line half associated with that memory element, the complement of that data signal is coupled to the other bit line half via the return line to increase the signal level differential across the sense amplifier.

Capacitive memory signal doubler cell

An extremely short channel Field Effect Transistor (FET) is made by making a first ion implant through a polysilicon mask aperture, converting the surface of the polysilicon into SiO.sub.2 to constrict the aperture size and then making a second ion implant of the opposite type impurity through the constricted aperture. The SiO.sub.2 growth effectively moves the edge of the mask by a small controlled distance. This permits a small controlled spacing between the two ion implants, which is used for defining an extremely short FET channel. Alternatively, a bipolar transistor with a narrow base zone can be made by analogous processing.

Method for making transistor structures

A dynamic capacitive memory cell having a storage node formed at the common junction of a fixed access capacitor and two MOS voltage variable capacitors. Data represented in the form of stored charge is written into the storage node through the fixed access capacitor under control of one of the MOS voltage variable capacitors and read out of the memory cell by a sensing device connected between the other voltage variable capacitor and ground. In another memory cell, one of the MOS voltage variable capacitors is replaced by an MOS transistor for preventing excess charge accumulation at the storage node.

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Cupertino, CA, United States of America

George Marr