Taiwan Semiconductor Manufacturing Comp. Ltd.

United Microelectronics Corp.

George Liu

Kuei Shun Chen

Vencent Chang

Norman Chen

Chin-Hsiang Lin

Chih-Yang Yeh

Tsiao-Chen Wu

Yao-Ching Ku

Te-Chih Huang

Hsiao-Tzu Lu

Ru-Gun Liu

Tsai-Sheng Gau

Wen-Chun Huang

Shang-Wen Chang

Benjamin Szu-Min Lin

Tsong-Hua Ou

Ying-Chou Cheng

Yu-Po Tang

Boren Luo

Wen-Hao Liu

Yu Lun Liu

Shu-Chen Lu

Cheng-Chung Chen

Harry-Hak-Lay Chuang

Bao-Ru Young

Tsung-Chieh Tsai

Vincent Chang

Chia-Ching Lin

Meng-Wei Chen

Jiann Yuan Huang

Hui-Ling Huang

Cheng Cheng Kuo

Meng Wei Chen

Yuhi-Jier Mii

Keui Shun Chen

Contrast enhancing exposure apparatus and method for use in semiconductor fabrication are described. In one embodiment, a method for forming a pattern on a substrate, wherein the substrate includes a photoresist layer comprising photoacid generators ('PAGs') and photobase generators ('PBGs'), is described. The method includes dividing the pattern into two component patterns; exposing the photoresist layer of the substrate to UV light through a first mask corresponding to a first one of the component patterns; subsequent to the exposing the photoresist layer of the substrate to UV light through the first mask, exposing the photoresist layer of the substrate to UV light through a second mask corresponding to a second one of the component patterns, wherein the PAGs and PBGs disposed in areas of the photoresist layer that have been exposed to UV light at least twice are activated and wherein the activated PAGs neutralize the activated PBGs in areas of the photoresist layer that have been exposed to UV light at least twice.

Contrast enhancing exposure system and method for use in semiconductor fabrication

Methods of forming a semiconductor structure and the semiconductor structure are disclosed. In one embodiment, a method includes forming a gate dielectric layer over a substrate, forming a gate electrode layer over the gate dielectric layer, and etching the gate electrode layer and the gate dielectric layer to form a horizontal gate structure and a vertical gate structure, wherein the horizontal gate structure and the vertical gate structure are connected by an interconnection portion. The method further includes forming a photoresist covering the horizontal gate structure and the vertical gate structure, with the photoresist having a gap exposing the interconnection portion between the horizontal gate structure and the vertical gate structure, and then etching the interconnection portion.

Controlling gate formation for high density cell layout

A method of forming a semiconductor structure includes forming a photoresist layer over a substrate. The photoresist layer includes a first material removable by a removal process. The first material at a guard band portion of the photoresist layer along an edge portion of the photoresist layer is converted to a second material. The second material is not removable by the removal process. Also, the first material at the edge portion of the photoresist layer is not converted to the second material. The guard band portion is farther from a periphery of the substrate than the edge portion. The removal process is performed to remove the first material after the conversion of the guard band portion.

Semiconductor structure and method and tool for forming the semiconductor structure

The method of patterning a photosensitive layer includes providing a substrate including a first layer formed thereon, treating the substrate including the first layer with cations, forming a first photosensitive layer over the first layer, patterning the first photosensitive layer to form a first pattern, treating the first pattern with cations, forming a second photosensitive layer over the treated first pattern, patterning the second photosensitive layer to form a second pattern, and processing the first layer using the first and second patterns as a mask.

Method for patterning a photosensitive layer

A method of patterning a semiconductor device including dividing a layout into more than one pattern. The method further includes depositing a film stack on a semiconductor substrate, depositing a hard mask on the film stack, and depositing a first photoresist on the hard mask. The method further includes patterning the first photoresist using a first pattern of the more than one pattern. The method further includes etching the hard mask to transfer a design of the first pattern of the more than one pattern to the hard mask. The method further includes depositing a second photoresist over the etched hard mask and patterning the second photoresist using a second pattern of the more than one pattern. The method further includes etching portions of the film stack exposed by a combination of the etched hard mask and the second photoresist.

Method of patterning a semiconductor device

An intensity selective exposure photomask, also describes as a gradated photomask, is provided. The photomask includes a first region including a first array of sub-resolution features. The first region blocks a first percentage of the incident radiation. The photomask also includes a second region including a second array of sub-resolution features. The second region blocks a second percentage of the incident radiation different that the first percentage. Each of the features of the first and second array includes an opening disposed in an area of attenuating material.

Intensity selective exposure photomask

A method for etching an ultra thin film is provided which includes providing a substrate having the ultra thin film formed thereon, patterning a photosensitive layer formed over the ultra thin film, etching the ultra thin film using the patterned photosensitive layer, and removing the patterned photosensitive layer. The etching process includes utilizing an etch material with a diffusion resistant carrier such that the etch material is prevented from diffusing to a region underneath the photosensitive layer and removing portions of the ultra thin film underneath the photosensitive layer.

Method for etching an ultra thin film

System and method for enhancing optical lithography methodology for hole patterning in semiconductor fabrication are described. In one embodiment, a photolithography system comprises an illumination system for conditioning light from a light source, the illumination system producing a three-pore illumination pattern; a reticle comprising at least a portion of a pattern to be imaged onto a substrate, wherein the three-pore illumination pattern produced by the illumination system is projected through the reticle; and a projection lens disposed between the reticle and the substrate.

Methodology for implementing enhanced optical lithography for hole patterning in semiconductor fabrication

An intensity selective exposure photomask, also describes as a gradated photomask, is provided. The photomask includes a first region including a first array of sub-resolution features. The first region blocks a first percentage of the incident radiation. The photomask also includes a second region including a second array of sub-resolution features. The second region blocks a second percentage of the incident radiation different that the first percentage.

The alignment mark and method for making the same are described. In one embodiment, a semiconductor structure includes a substrate having a device region and an alignment region; a first shallow trench isolation (STI) feature in the alignment region and having a first depth D; a second STI feature in the device region and having a second depth D; an alignment mark with patterned features overlying the first STI in the alignment region; and a gate stack formed on an active region in the device region.

System and method for providing alignment mark for high-k metal gate process

Provided is a semiconductor device. The device includes a substrate having a photo acid generator (PAG) layer on the substrate. The PAG layer is exposed to radiation. A photoresist layer is formed on the exposed PAG layer. The exposed PAG layer generates an acid. The acid decomposes a portion of the formed photoresist layer. In one embodiment, the PAG layer includes organic BARC. The decomposed portion of the photoresist layer may be used as a masking element.

Pattern formation in semiconductor fabrication

A gradated photomask is provided. The photomask includes a first region including a first plurality of sub-resolution features and a second region including a second plurality of sub-resolution features. The first region blocks a first percentage of the incident radiation. The second region blocks a second percentage of the incident radiation. The first and second percentage are different. An intensity selective exposure method is also provided.

Intensity selective exposure method and apparatus

Photolithography processing methods by which a photoresist layer is deposited, a portion of the photoresist layer is exposed to electromagnetic radiation to transfer a reticle pattern thereto, and the exposed portion of the photoresist layer is treated with thermal energy while being subjected to an electric field, wherein the electric field is configured to substantially limit diffusion of the exposed photoresist layer portion to anisotropic diffusion.

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Shin-Chu, Taiwan

George Liu