Trw Limited

USA As Represented by Secretary of the Navy

Northrop Grumman Systems Corporation

Other

Linear Measurements, Inc.

George L Kerber

Lynn A Abelson

Raffi N Elmadjian

Eric G Ladizinsky

Quentin P Herr

Edward C Jelks

Michael Leung

Harper J Whitehouse

William D Squire

Howard A Wilcox

A superconductor integrated circuit () includes an anodization ring () disposed around a perimeter of a tunnel junction region () for preventing a short-circuit between an outside contact () and the base electrode layer (). The tunnel junction region () includes a junction contact () with a diameter of approximately 1.00 &#x3bc;m or less defined by a top surface of the counter electrode layer (). The base electrode layer () includes an electrode isolation region () disposed approximately 0.8 &#x3bc;m in horizontal distance from the junction contact () for providing device isolation.

Self-aligned junction passivation for superconductor integrated circuit

The self inductance associated with a capacitance A in a superconductor integrated circuit (FIG. ) is reduced by adding a layer of superconductor metal (A ) overlying the capacitor, effectively producing a negative inductance to counteract the self-inductance of the capacitor leads, thereby reducing inductance of the circuit. As a result it possible to transfer a single flux quantum (&ldquo;SFQ&rdquo;) pulse through the capacitor. Capacitors ( and FIG. ) of the foregoing type are incorporated in superconductor integrated circuit SFQ transmission lines (FIG. ) to permit SQUID-to-SQUID transfer of SFQ pulses, while maintaining the circuit grounds of the respective SQUIDs in DC isolation. Bias current ( ) may be supplied to multiple SQUIDs ( & & FIG. ) serially, reducing the supply current required previously for operation of multiple SQUIDs.

Capacitor for signal propagation across ground plane boundaries in superconductor integrated circuits

A method for fabricating an integrated circuit which reduces steps in the integrated circuit comprising the steps of depositing a first conductive material layer over the first dielectric material layer and patterning the first conductive material layer to form a first conductive pattern. A second dielectric layer is then deposited over the first conductive pattern and the exposed portions of the first dielectric material layer. A planarizing material layer is applied over the second dielectric material layer and cured such that the planarizing material layer produces a substantially planar top surface. The planarizing material layer and portions of the second dielectric material layer are removed in a manner which maintains the substantially planar top surface until only a preselected amount of material remains over the first conductive pattern.

Method for fabricating a microelectronic integrated circuit with improved step coverage

The invention is a process for reducing roughness of a surface of a superconductor material ( ) having an undesirable surface roughness ( and ) and a trilayer superconductor integrated circuit ( ). The process for reducing roughness of a surface of superconductor material having an undesirable surface roughness includes coating the surface with an oxide layer ( ) to fill the undesirable surface roughness and to produce an exposed oxide surface ( ) with a roughness less than the surface roughness; and etching the exposed oxide surface to remove a thickness of the oxide layer followed by removing at least a portion of the oxide layer filling the undesirable surface roughness and a portion of the surface of the superconductor material to produce an exposed etched surface ( ) comprised of at least the superconductor material which has a surface roughness less than the undesirable surface roughness.

Process for reducing surface roughness of superconductor integrated circuit having a ground plane of niobium nitride of improved smoothness

A high-temperature (10 K) superconductive integrated circuit has a ground plane (,), an interlevel dielectric (,), and a low value resistor (,) to provide conductive paths to reduce parasitic circuit inductances, thereby increasing the speed and performance of the integrated circuit. The circuit also includes a high value resistor (,) connected between interconnect wires (,) to produce a desired resistance with a short distance between the interconnect wires (,), thereby significantly reducing the circuit area. A method of fabricating the integrated circuit includes depositing the interlevel dielectric (,) on the ground plane (,) in separate steps, depositing and etching the trilayer (,), etching the low value resistor (,) on the dielectric (,), depositing the high value resistor (,) at substantially the same level above the ground plane (,) as the interconnect wires (,) of the first wire layer (,), and etching the interconnect wires (,) of the second wire layer (,) on the high value resistor (,).

Low inductance superconductive integrated circuit and method of fabricating the same

The invention is a process for reducing roughness of a surface of a superconductor material (23) having an undesirable surface roughness (30 and 32) and a trilayer superconductor integrated circuit (100). The process for reducing roughness of a surface of superconductor material having an undesirable surface roughness includes coating the surface with an oxide layer (40) to fill the undesirable surface roughness and to produce an exposed oxide surface (42) with a roughness less than the surface roughness; and etching the exposed oxide surface to remove a thickness of the oxide layer followed by removing at least a portion of the oxide layer filling the undesirable surface roughness and a portion of the surface of the superconductor material to produce an exposed etched surface (44) comprised of at least the superconductor material which has a surface roughness less than the undesirable surface roughness.

Process for reducing surface roughness of superconductor integrated

A high-temperature (10 K) superconductive integrated circuit has a ground plane (2), an interlevel dielectric (6), and a low value resistor (18) to provide conductive paths to reduce parasitic circuit inductances, thereby increasing the speed and performance of the integrated circuit. The circuit also includes a high value resistor (20) connected between interconnect wires (34) to produce a desired resistance with a short distance between the interconnect wires (34), thereby significantly reducing the circuit area. A method of fabricating the integrated circuit includes depositing the interlevel dielectric (6) on the ground plane (2) in separate steps, depositing and etching the trilayer (12, 14, 16), etching the low value resistor (18) on the dielectric (6), depositing the high value resistor (20) at substantially the same level above the ground plane (2) as the interconnect wires (22) of the first wire layer (24), and etching the interconnect wires (34) of the second wire layer (32) on the high value resistor (20).

Low inductance superconductive integrated circuit and method of

A high-temperature (10K) superconductive integrated circuit has a ground plane (2), an interlevel dielectric (6), and a low value resistor (18) to provide conductive paths to reduce parasitic circuit inductances, thereby increasing the speed and performance of the integrated circuit. The circuit also includes a high value resistor (20) connected between interconnect wires (34) to produce a desired resistance with a short distance between the interconnect wires (34), thereby significantly reducing the circuit area. A method of fabricating the integrated circuit includes depositing the interlevel dielectric (6) on the ground plane (2) in separate steps, depositing and etching the trilayer (12, 14, 16), etching the low value resistor (18) on the dielectric (6), depositing the high value resistor (20) at substantially the same level above the ground plane (2) as the interconnect wires (22) of the first wire layer (24), and etching the interconnect wires (34) of the second wire layer (32) on the high value resistor (20).

Low inductance superconductive integrated circuit

A relatively simple circuit for implementing a low-cost, low power, highly accurate capacitance-to-voltage converter by which to measure the unknown capacitance of a capacitor. The circuit is characterized by the ability to eliminate error due to stray capacitance sources. The circuit is implemented by a crystal controlled clock generator which produces multi-phase clock signals to control the operation of a pair of series connected field effect transistors and a buffer amplifier. The field effect transistors are alternately switched on and off to periodically charge and discharge the capacitor under measurement between a source of reference potential and the inverting input terminal of a precision operational amplifier. The output voltage of the operational amplifier tracks the capacitance of the capacitor under measurement, such that an accurate indication of its capacitance is obtained by merely reading the output of the operational amplifier.

High accuracy direct reading capacitance-to-voltage converter

A method and the resulting article for providing a nearly zero temperature coefficient pressure transducer preferably comprising a cylindrical capacitor whose capacitance is a function of both externally applied pressure and, undesirably, of temperature. The variation of capacitance with temperature may be greatly minimized by selectively choosing a transducer material characterized by particular parameter constants such that the temperature coefficient of Young's modulus (.alpha..sub.E) is equal in magnitude but opposite in sign to the temperature coefficient of linear expansion (.alpha..sub.l). Moreover, the thermal variation of capacitance can be further minimized by selectively choosing a transducer material whose temperature coefficient of linear expansion and of Young's modulus are nearly zero. Fabricating a capacitance pressure transducer from materials characterized by .alpha..sub.E and .alpha..sub.l which are both equal and opposite in sign and/or very small in magnitude will greatly reduce the high pressure, temperature sensitivity of the transducer, especially when compared with the temperature sensitivity under pressure characteristics of conventional fused quartz pressure transducers.

Method and article for a nearly zero temperature coefficient pressure

A capacitance pressure transducer comprising two fused quartz cylinders concentrically aligned with and separated from one another so that a small gap is established therebetween. The capacitance of the transducer is determined by the size of the gap and the length of capacitor electrodes which are disposed within the gap. Changes in capacitance are measured by an external circuit which is connected to the electrodes. The electrodes are attached to respective opposing surfaces of the inner and outer cylinders and responsive to pressure induced changes in the size of the gap. The cylinders are connected together by means of a unique joint formed between respective first ends thereof, so that the inner disposed cylinder is adapted to be cantilevered from the joint and suspended within the outer cylinder. That is, the first ends of each cylinder are formed with an identical taper. The inner cylinder is located within the outer cylinder, such that the respective first ends thereof form a close or flush fit relative to one another. The joint to bond the first cylinder ends together is formed by a metal (e.g. titanium) hydride solder process. A fused quartz-to-fused quartz seal is formed by the steps of supplying a mixture of an indium alloy solder and titanium hydride to the first ends of the inner and outer cylinders and heating the cylinders in a vacuum chamber. The titanium hydride acts as a flux for promoting a continuous and reliable solder joint between the first cylinder ends.

Capacitance pressure transducer and method of fabrication therefor

A high performance, low cost filter having a capacitor electrically connected therein to effectively block electromagnetic noise signals that are generated by certain electrical and electromechanical devices, including an electric motor, such as that commonly associated with either of the engine of a motor vehicle or a household appliance. In one embodiment of the invention, the filter is provided in combination with a fuse link that is particularly structured to have both relatively low inductance and low fusing current characteristics. The capacitor and the fuse link may be contained within a filter housing. Moreover, both the capacitor and the fuse link may be flexibly mounted within the filter housing, to thereby reduce the application of mechanical stresses and minimize the likelihood of possible damage thereto during the handling and installation of the filter. In the assembled relationship, the filter housing is particularly structured so that a portion thereof containing the capacitor can be located exterior to the housing of the electrical or electromechanical device from which electromagnetic noise is generated, so as to reduce the amount of heat to which the filter capacitor is subjected during operation of the device. In another embodiment of the invention, a low inductance fuse is fabricated (apart from in combination with the aforementioned filter) by means of strip line transmission line techniques and interconnected between a source and a load of an electrical or electromechanical system.

Combination low inductance fuse and electromagnetic noise filter

Planar superconducting-normal-superconducting (SNS) Josephson microbridges nd superconducting quantum interference devices (SQUIDs) with bridge widths of about 0.2 microns and lengths of about 0.1 micron or less are fabricated with the aid of a technique referred to as 'shadow evaporation'. The procedure permits the submicron dimensions to be set by edge film thickness and slant evaporation angle, both of which can be accurately measured. Microbridges have been constructed with vanadium banks or electrodes and gold-titanium bridges, although other materials can be used including superconducting metals for the bridge. It is expected that a refined version of this technique would be suitable for repeated batch fabrication of single and multiple Josephson microbridges.

Growing community of inventors

San Diego, CA, United States of America

George L Kerber