Monolithic Memories, Inc.

George L Geannopoulos

Mark E Fitzpatrick

Cyrus Y Tsui

Robert J Bosnyak

Andy Chan

Michael G France

Steve Y Chan

A circuit constructed in accordance with this invention includes means for asynchronously forcing a flip-flop (70) or a register to a programmable logical state in response to an initialization input signal (I). In one embodiment, a D-type flip-flop (70) is provided having data input terminal (71), a clock input terminal (77), a data output terminal (103), an initialization input terminal (41), and a programming input terminal (11). When an initialization input signal I is received, a predefined output signal is immediately placed on the data output terminal (103). The predefined output signal is defined by the status of a fuse (13), which is opened, if desired, via the programming input terminal (11). When an initialization input signal is not received, the flip-flop (70) operates as a normal D-type flip-flop.

Programmable asynchronous register initialization circuit

The present invention combines in either a logical AND function of N logical input signals, where N is a selected positive integer greater than or equal to 1, and provides programmably, either a direct AND output signal or a NAND output signal. The invention accomplishes this using a minimum number of components in the data path, between the logical input leads and logical output leads. A minimum of components in the data path reduces the propagation delay introduced by the circuit. The invention accomplishes this by providing two AND gates connected to the same set of N logical input signals. The output signal of one AND gate is inverted by an inverter with an enable/disable input lead. The output signal of the other AND gate is inverted twice by two inverters. The second inverter has an enable/disable input lead. Means are provided for exclusively enabling one or the other of the two inverters with an enable/disable input lead. Thus, either the once inverted signal is provided to the output lead or the twice inverted signal is provided to the output lead.

Fast and gate with programmable output polarity

Growing community of inventors

San Jose, CA, United States of America

George L Geannopoulos