Intel Corporation

George L Geannopoulos

J Keith Hodgson

Fabrice Paillet

Jonathan P Douglas

David E Duarte

Gregory F Taylor

Avner Kornfeld

Takao Oshita

James S Ayers

Gerhard Schrom

Edward Allyn Burton

Keng L Wong

Joseph Shor

Alexander Lyakhov

Greg F Taylor

Ravi Sankar Vunnam

Larry E Mosley

Xia Dai

Oleg Dadashev

William Dawson Kesling

Usman Mughal

Samie B Samaan

Narayanan Natarajan

Narayanan Raghuraman

Hong-Piao Ma

Chiu Keung Tang

Mathew B Nazareth

Kedar Mangrulkar

Hong Yun Tan

Venkatesh Prasanna

Michael W Rogers

Lan D Vu

Niraj Bindal

Described is an analog to digital converter (ADC) which comprises: a sigma-delta modulator to receive an analog signal, the sigma-delta modulator operable to perform chopping to cancel common-mode noise; and one or more counters coupled to the sigma-delta modulator to generate a digital code representative of the analog signal.

Low power analog to digital converter

Described is an apparatus which comprises: a bandgap core to provide a control signal; and an output stage coupled to the bandgap core, the output stage to receive the control signal and to provide a low impedance output at an output node.

Bandgap reference circuit with low output impedance stage and power-on detector

Described is an apparatus having a non-linear control to manage power supply droop at an output of a voltage regulator. The apparatus comprises: a first inductor for coupling to a load; a capacitor, coupled to the first inductor, and for coupling to the load; a first high-side switch couple to the first inductor; a first low-side switch coupled to the first inductor; a bridge controller to control when to turn on and off the first high-side and first low-side switches; and a non-linear control (NLC) unit to monitor output voltage on the load, and to cause the bridge controller to turn on the first high-side switch and turn off the first low-side switch when a voltage droop is detected on the load.

Non-linear control for voltage regulator

Described is a linear voltage regulator circuit comprising a first voltage regulator comprising a first source follower having a first node to provide a first power supply, and a second node different from the first node; and a second voltage regulator comprising a second source follower having a first node to provide a second power supply, and a second node different from the first node, wherein the second nodes of the first and second voltage regulators are electrically shorted.

Linear voltage regulator based on-die grid

Described is an apparatus to trim on-die passive components. The apparatus comprises: a resistor-capacitor (RC) dominated oscillator independent of first order transistor speed dependency, wherein the RC dominated oscillator including one or more resistors and capacitors with programmable resistance and capacitance, and wherein the RC dominated oscillator to generate an output signal having a frequency depending substantially on values of the programmable resistance and capacitance; and a trim-able resistor or capacitor operable to be trimmed, for compensating process variations, according to a program code associated with the programmable resistance and capacitance of the RC dominated oscillator.

On-die trim-able passive components for high volume manufacturing

An embodiment of the present invention is a technique for thermal sensing. A sensing structure generates a response according to a local temperature at a first location on a die. A sensor core coupled to the sensing structure via routing lines to provide a measurement of the local temperature from the response. The sensor core is located at a second location remote to the first location and is powered by an analog supply voltage source located in a vicinity of the second location.

Accurate on-die temperature measurement using remote sensing

A clock generating circuit is provided that includes a multiplexing device coupled to a clock distribution network to select between a synchronous mode and an asynchronous mode. The device may also include a plurality of distributed ring oscillators to drive the clock distribution network in the asynchronous mode. In the synchronous mode, the multiplexing device may pass a signal from a phase lock loop circuit located external to a core.

Clock generating circuit and method

An integrated circuit having a first plurality of wire bond pads located along a horizontal axis, a second plurality of wire bond pads located along a vertical axis, and a plurality of C4 pads arranged in a grid array wherein each grid is defined by the intersection of one of the first wire bond pads and one of the second wire bond pads.

Integrated circuit device having C4 and wire bond connections

An apparatus for deskewing clock signals in a synchronous digital system. The apparatus contains a phase detection circuit that receives a plurality of clock signals and generates an output based on a phase relationship between those clock signals. A controller then receives the output of the phase detector and determines which one of the plurality of clock signals requires adjustment based on the output of the phase detector and a bit from a delay shift register. The controller transmits a delay signal to one of a plurality of delay circuits which modifies the delay of the clock signal that the controller determined to require adjustment.

Method and apparatus for deskewing clock signals

An apparatus that efficiently delivers electrical power and lowers the inductance to an integrated circuit. In one embodiment, the present invention includes an apparatus for delivering electrical power to an integrated circuit comprising two planes, substantially parallel to one another, having many ground and power traces. The ground and power traces of the separate planes are connected together and connected to the integrated circuit, thereby providing power to the integrated circuit. In each individual plane, the ground and power traces are substantially parallel to each other, one array of traces in one plane substantially perpendicular to another array of traces in another plane. The apparatus being electrically coupled to a printed circuit board having at least one decoupling capacitor with first and second electrodes coupled to at least two of the ground and power connections, respectively, of the integrated circuit through the printed circuit board, and the first and second ground and power planes.

Semiconductor package substrate with power die

The reset circuit includes a first current mirror coupled to a first terminal of a power supply. A second current mirror is coupled to a second terminal of the power supply. First and second switches couple the first current mirror to the second current mirror. A threshold detector provides a first signal when a current differential between the first and second current mirrors exceeds a predetermined threshold. A first shunt shunts the first current mirror to the first terminal. A second shunt shunts the second current mirror to the second terminal. Buffering circuitry controls the first and second switches and the first and second shunts in response to the first signal. The buffering circuitry further provides a buffered reset signal from the first signal. The buffered reset signal transitions from a first level to a second level in response to the first signal. The switches and shunts reduce the biases on the threshold detector and current mirrors.

Power up reset circuit with threshold voltage shift protection

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Portland, OR, United States of America

George L Geannopoulos