Motorola Corporation

Freescale Semiconductor,inc.

Delco Electronics Corporation

George L Espinor

Bruce L Morton

James M Sibigtroth

Michael C Wood

Michael I Catherwood

Ko-Min Chang

Kuo-Tung Chang

Mark R Heene

Craig A Cavins

William L Lucas

Michael H Menkedick

A low voltage detection (LVD) system for a logic device includes a first LVD circuit () to provide an indicator when a supply pin voltage () falls below a first voltage level, and a second LVD circuit () to provide an interrupt () when the supply pin voltage falls below a second voltage level. In one embodiment, the second LVD circuit consumes more power than the first LVD circuit, and is therefore selectively enabled. In one embodiment, when the supply pin voltage is between the first and second voltage levels and the logic device is in a stop or low power mode, the second LVD circuit is periodically enabled to monitor the supply pin voltage. After the supply pin voltage falls below the second voltage level, the logic device is placed in a safe state where the logic device is inhibited from acknowledging interrupts until the supply pin voltage rises above the first voltage level.

Low voltage detection system

A data processing system () has an embedded non-volatile memory () that is programmed and erased by use of a high voltage provided by a charge pump (). In order to prevent the non-volatile memory () from being inadvertently programmed or erased during low power supply voltage conditions, the charge pump () is disabled and discharged when the power supply voltage drops below a predetermined value. This is accomplished by enabling a low voltage detect circuit () in response to a program or erase operation being initiated. A control register () will provide a high voltage enable signal to the charge pump () only when a power supply valid signal is received. In another embodiment, the low voltage detect circuit () may be enabled by another condition to protect the data processing system () from an authorized access.

Method and apparatus for protecting an integrated circuit from erroneous operation

A single memory array () has an isolation circuit for isolating segments of a same bit line (SegBL, SegBL) from each other. The isolation circuit () permits memory cells located in one segment () of an array to be read while memory cells of another segment () of the array are being erased. In one example, the isolation circuit () electrically couples the segments during a read or program of memory cells located on the second segment (SegBL). Program information stored in the single memory array may always be accessed while a portion of the same array is erased. Dynamic variation of the size of the isolated bit line segment occurs when multiple isolation circuits are used to create more than two array segments.

Memory bit line segment isolation

Method and apparatus for providing erasing and programming protection of an EEPROM (22) to significantly reduce the possibility of unintentional erasing or programming of the EEPROM (22). In one embodiment, a read access of a block protect value (111) is a requirement for enabling the EEPROM charge pump (78). The block protect value (111) may be located in the EEPROM array (22) itself. In one embodiment, an externally provided signal (24) must be provided to an integrated circuit (10) in order to enable a write access to modify the block protect value (111). In one embodiment, a charge pump enable value (103) is provided to enable or disable operation of the charge pump (78). Thus, a combination of hardware and software protection is provided for an EEPROM (22), including protection for enabling of a charge pump (78).

Method and apparatus for providing erasing and programming protection

A memory array (25) having a selected memory cell (10) and an unselected memory cell (30) is programmed and read. Each memory cell in the memory array (25) contains an isolation transistor (22) and a floating gate transistor (23). To program the selected memory cell (10), programming voltages are applied to a control gate line (21), a drain line (14), an isolation line (19), and a source line (12). To reduce the effects of the drain disturb problem, a gate terminal (32) of the unselected memory cell (30) is held at a positive voltage. To read selected memory cell (10), a read voltage is applied to an isolation gate line (31) of unselected memory cell (30) which insures that the unselected memory cell (30) does not conduct or contribute to leakage current and power consumption during the read operation.

Method for operating a memory array

A data processor (20) includes a nonvolatile memory system (25) which stores not only normal program memory (31), but also mask option bits (32), within a common array (30) of nonvolatile memory cells. A control circuit (40) of the nonvolatile memory system (25) detects when a central processing unit (21) is accessing the program memory (31). In response to either an end of reset signal or a refresh request signal, the control circuit (40) copies the mask option bits (32) into a volatile mask option register (44) only when the central processing unit (21) is not accessing the program memory (31). Otherwise, the control circuit (40) holds off the access to the mask option bits (32). The mask option register (44) provides signals to various circuits (28) to control their operation. Thus, the mask option bits (32) may be stored in nonvolatile form in the same array (30) as the program memory (31), enhancing reliability and reducing integrated circuit size.

Data processor having operating modes selected by at least one mask

A single chip microcomputer with patching and configuration is provided with blocks of patch memory which may be patched over faulty and/or obsolete areas of the microcomputer's memory map under control of starting address registers which are implemented in on-board non-volatile memory. The starting address registers, and enable registers which control whether each patch block is placed in the memory map, are programmable under control of the microcomputer's CPU. Newly programmed values in these registers are not effective to alter the memory map until a reset sequence enables a latch. In particular embodiments, patch blocks may overlie mask ROM, internal EPROM and/or EEPROM, external memory or devices or any other desireable portion of the memory map.

Growing community of inventors

Austin, TX, United States of America

George L Espinor