International Business Machines Corporation

Globalfoundries Inc.

George L Chiu

Thomas Mario Cipolla

Paul William Coteus

Rama Nand Singh

Alan G Gara

Janusz S Wilczynski

Todd Edward Takken

Fuad Elias Doany

Lawrence Shungwei Mok

Matthias Augustin Blumrich

Gerard Vincent Kopcsay

Valentina Salapura

Philip Heidelberger

Mark Edwin Giampapa

Dong Chen

Alan Edward Rosenbluth

Derek Brian Dove

Warren Edward Maule

Daniel Mark Dreps

Kevin Charles Gower

Russell Alan Budd

Hillery C Hunter

Martin Ohmacht

Alexandre E Eichenberger

Charles Arthur Kilmer

Shawn Anthony Hall

Krishnan Sugavanam

Rudolf Adriaan Haring

Kyu-Hyoun Kim

Michael K Gschwind

Michael A Blocksome

Joseph D Ratterman

Adam James Muff

Bruce Martin Fleischer

Thomas M Gooding

Robert William Wisniewski

John A Gunnels

Burkhard Steinmacher-Burow

Kathryn Mary O'Brien

Mark Gregory Megerian

Sameh W Asaad

Thomas Winters Fox

John Kevin O'Brien

Chen-Yong Cher

Barry Marshall Trager

Peng Wu

Dong Chen Chen

Charles David Wait

Sameer Kumar

James Anthony Marcella

Todd Alan Inglett

Jeffrey John Parker

Robert Matthew Senger

Noel A Eisley

Dale J Pearson

David L Satterfield

Douglas R Miller

Craig Brian Stunkel

Yutaka Sugawara

Amith R Mamidala

Kristan D Davis

Jose R Brunheroto

Michael B Mundy

Matthew Roger Ellavsky

Robert E Walkup

James Lee Van Oosten

Samuel J Miller

Ruth Janine Poole

Gabor J Dozsa

Ralph E Bellofatto

Peter Boyle

Brant L Knudson

Norman Christ

Kahn C Evans

William Maupin Stockdell

Alfred Thomas Watson, Iii

Brian E Smith

John Peter Karidis

Gareth Geoffrey Hougham

James Patrick Doyle

John K P O'Brien

Michael James Cordes

Jean-Marc Halbout

Steven Allen Cordes

Thomas Ainsworth, Jr

Mark E Giampap

Philip Heidlberger

Todd E c/o Ibm United Kingdom Limited Takken

Gerald V Kopscay

Dong c/o Ibm United Kingdom Limited Chen

A Multi-Petascale Highly Efficient Parallel Supercomputer of 100 petaflop-scale includes node architectures based upon System-On-a-Chip technology, where each processing node comprises a single Application Specific Integrated Circuit (ASIC). The ASIC nodes are interconnected by a five dimensional torus network that optimally maximize the throughput of packet communications between nodes and minimize latency. The network implements collective network and a global asynchronous network that provides global barrier and notification functions. Integrated in the node design include a list-based prefetcher. The memory system implements transaction memory, thread level speculation, and multiversioning cache that improves soft error rate at the same time and supports DMA functionality allowing for parallel processing message-passing.

Multi-petascale highly efficient parallel supercomputer

The present disclosure relates generally to a dedicated memory structure (that is, hardware device) holding data for detecting available worker thread(s) and informing available worker thread(s) of task(s) to execute.

Dedicated memory structure holding data for detecting available worker thread(s) and informing available worker thread(s) of task(s) to execute

A Multi-Petascale Highly Efficient Parallel Supercomputer of 100 petaOPS-scale computing, at decreased cost, power and footprint, and that allows for a maximum packaging density of processing nodes from an interconnect point of view. The Supercomputer exploits technological advances in VLSI that enables a computing model where many processors can be integrated into a single Application Specific Integrated Circuit (ASIC). Each ASIC computing node comprises a system-on-chip ASIC utilizing four or more processors integrated into one die, with each having full access to all system resources and enabling adaptive partitioning of the processors to functions such as compute or messaging I/O on an application by application basis, and preferably, enable adaptive partitioning of functions in accordance with various algorithmic phases within an application, or if I/O or other processors are underutilized, then can participate in computation or communication nodes are interconnected by a five dimensional torus network with DMA that optimally maximize the throughput of packet communications between nodes and minimize latency.

A performance monitoring unit (PMU) and method for monitoring performance of events occurring in a multiprocessor system. The multiprocessor system comprises a plurality of processor devices units, each processor device for generating signals representing occurrences of events in the processor device, and, a single shared counter resource for performance monitoring. The performance monitor unit is shared by all processor cores in the multiprocessor system. The PMU is further programmed to monitor event signals issued from non-processor devices.

Shared performance monitor in a multiprocessor system

A novel massively parallel supercomputer of hundreds of teraOPS-scale includes node architectures based upon System-On-a-Chip technology, i.e., each processing node comprises a single Application Specific Integrated Circuit (ASIC). Within each ASIC node is a plurality of processing elements each of which consists of a central processing unit (CPU) and plurality of floating point processors to enable optimal balance of computational performance, packaging density, low cost, and power and cooling requirements. The plurality of processors within a single node individually or simultaneously work on any combination of computation or communication as required by the particular algorithm being solved. The system-on-a-chip ASIC nodes are interconnected by multiple independent networks that optimally maximizes packet communications throughput and minimizes latency. The multiple networks include three high-speed networks for parallel algorithm message passing including a Torus, Global Tree, and a Global Asynchronous network that provides global barrier and notification functions.

Massively parallel supercomputer

An advanced memory having improved performance, reduced power and increased reliability. A memory device includes a memory array, a receiver for receiving a command and associated data, error control coding circuitry for performing error control checking on the received command, and data masking circuitry for preventing the associated data from being written to the memory array in response to the error control coding circuitry detecting an error in the received command. Another memory device includes a programmable preamble. Another memory device includes a fast exit self-refresh mode. Another memory device includes auto refresh function that is controlled by the characteristic device. Another memory device includes an auto refresh function that is controlled by a characteristic of the memory device.

Advanced memory device having improved performance, reduced power and increased reliability

A novel massively parallel supercomputer of hundreds of teraOPS-scale includes node architectures based upon System- On-a-Chip technology, i.e., each processing node comprises a single Application Specific Integrated Circuit (ASIC). Within each ASIC node is a plurality of processing elements each of which consists of a central processing unit (CPU) and plurality of floating point processors to enable optimal balance of computational performance, packaging density, low cost, and power and cooling requirements. The plurality of processors within a single node individually or simultaneously work on any combination of computation or communication as required by the particular algorithm being solved. The system-on-a-chip ASIC nodes are interconnected by multiple independent networks that optimally maximizes packet communications throughput and minimizes latency. The multiple networks include three high-speed networks for parallel algorithm message passing including a Torus, Global Tree, and a Global Asynchronous network that provides global barrier and notification functions.

A performance monitoring unit (PMU) and method for monitoring performance of events occurring in a multiprocessor system. The multiprocessor system comprises a plurality of processor devices units, each processor device for generating signals representing occurrences of events in the processor device, and, a single shared counter resource for performance monitoring. The performance monitor unit is shared by all processor cores in the multiprocessor system. The PMU comprises: a plurality of performance counters each for counting signals representing occurrences of events from one or more the plurality of processor units in the multiprocessor system; and, a plurality of input devices for receiving the event signals from one or more processor devices of the plurality of processor units, the plurality of input devices programmable to select event signals for receipt by one or more of the plurality of performance counters for counting, wherein the PMU is shared between multiple processing units, or within a group of processors in the multiprocessing system. The PMU is further programmed to monitor event signals issued from non-processor devices.

A massively parallel supercomputer of petaOPS-scale includes node architectures based upon System-On-a-Chip technology, where each processing node comprises a single Application Specific Integrated Circuit (ASIC) having up to four processing elements. The ASIC nodes are interconnected by multiple independent networks that optimally maximize the throughput of packet communications between nodes with minimal latency. The multiple networks may include three high-speed networks for parallel algorithm message passing including a Torus, collective network, and a Global Asynchronous network that provides global barrier and notification functions. These multiple independent networks may be collaboratively or independently utilized according to the needs or phases of an algorithm for optimizing algorithm processing performance. The use of a DMA engine is provided to facilitate message passing among the nodes without the expenditure of processing resources at the node.

Ultrascalable petaflop parallel supercomputer

A novel massively parallel supercomputer of hundreds of teraOPS-scale includes node architectures based upon System-On-a-Chip technology, i.e., each processing node comprises a single Application Specific Integrated Circuit (ASIC). Within each ASIC node is a plurality of processing elements each of which consists of a central processing unit (CPU) and plurality of floating point processors to enable optimal balance of computational performance, packaging density, low cost, and power and cooling requirements. The plurality of processors within a single node may be used individually or simultaneously to work on any combination of computation or communication as required by the particular algorithm being solved or executed at any point in time. The system-on-a-chip ASIC nodes are interconnected by multiple independent networks that optimally maximizes packet communications throughput and minimizes latency. In the preferred embodiment, the multiple networks include three high-speed networks for parallel algorithm message passing including a Torus, Global Tree, and a Global Asynchronous network that provides global barrier and notification functions. These multiple independent networks may be collaboratively or independently utilized according to the needs or phases of an algorithm for optimizing algorithm processing performance. For particular classes of parallel algorithms, or parts of parallel calculations, this architecture exhibits exceptional computational performance, and may be enabled to perform calculations for new classes of parallel algorithms. Additional networks are provided for external connectivity and used for Input/Output, System Management and Configuration, and Debug and Monitoring functions. Special node packaging techniques implementing midplane and other hardware devices facilitates partitioning of the supercomputer in multiple networks for optimizing supercomputing resources.

Three component color sub-pixel element areas of red,green and blue, are serially formed in an overall pixel area, on a transparent substrate, and after each individual color sub pixel element formation, a layer of protective transparent material is applied over the individual sub pixel element and the pixel area before formation of the next sub pixel element. The protective layers render the sub pixel elements unaffected by the processing of subsequent sub pixel members where such conditions as high temperature curing, hardening agents or hardening processes are involved, whereby advantages are achieved in manufacturability, reliability, yield, cost, and throughput.

Color filters formed sequentially with intervening protective films for

A stand for a portable personal computer including a base including a front side, a back side, a right side, a left side, and a bottom surface. The stand includes at least one stand member interconnectable with the base. The at least one stand member is positionable in a deployed position and a stowed position. In the deployed position the at least one stand member supports at least one portion of the bottom surface of the base at an elevated level with respect to a surface that the portable personal computer is supported by. The at least one stand member engages a surface of the base in the stowed position.

Portable computer stand for enhanced cooling

An arrangement and method for enhancing the cooling capacity of portable personal computers. The power dissipation of portable personal computers, especially such as laptop computers or the like, is enhanced through the utilization of a split swivable keyboard adapted to provide for an increased cooling surface area for electronic components generating heat during use of the computer.

Computer keyboard with enhanced cooling and touch pad

Growing community of inventors

Cross River, NY, United States of America

George L Chiu