Texas Instruments Corporation

George L Brantingham

Richard H Wiggins, Jr

Paul S Breedlove

James H Moore

Louis H Phillips

Larry T Novak

Gene A Frantz

Perry Wyan Lou

Graham S Tubbs

Christopher Slawinski

Richard A Houghton

Jeffrey R Teza

Steven J Easley

Warren S Graber

Lawrence J Housey, Jr

An inductive coupled object identification system (FIGS. 2a and 2b) uses inductive coupling to detect and identify objects. Each object includes an object resonance circuit (LT/CT) with a unique object resonance frequency. Base electronics (50) includes an inductive-coupling base coil (L1) coupled to an oscillator circuit (60). To detect an object, the oscillator circuit continually sends START pulses to the base coil. When an object is proximate to the base coil, a START pulse is inductively coupled to the object resonance circuit, causing it to resonate at the object resonance frequency. This resonance condition is detected by the oscillator circuit, which outputs an oscillation signal FREQ at the object resonance frequency. Frequency counting logic (70) is used to determine the object resonance frequency, allowing a microcomputer (80) to identify the object. Two embodiments of the object identification system are described: a dynamic embodiment (FIGS. 1a and 1b) in which ball-shaped objects (10) are dropped into a bowl (13) through a single base coil (L1) in the rim of the bowl, and a static embodiment (FIGS. 1c and 1d) in which ring-shaped objects (20) are placed over a post (23) incorporating multiple base coils (L1-L5). For the static embodiment, the multiple base coils are multiplexed by a base coil selector circuit (FIG. 2b, 100).

Inductive coupled object identification system and method

An electronic hand-held, talking learning aid is disclosed. The learning aid includes a MOS speech synthesizer chip having an active surface area on the order of 45,000 square mils. The disclosed speech synthesizer chip includes a digital lattice filter, a voiced/unvoiced excitation circuit, a speech parameter interpolator, an input parameter decoder, a digital-to-analog converter and associated timing circuits. The learning aid is also provided with a microprocessor which functions as a controller for controlling the operation of the unit. A small speaker is driven by the digital-to-analog converter on the speech synthesis chip and a keyboard and display device are strobed by the microprocessor controller. Features include modes in which a speech synthesizer recites instructions or questions to the operator who must properly respond.

Learning aid or game having miniature electronic speech synthesis chip

An electronic handheld talking translator including a speech synthesis integrated circuit device. The speech synthesis integrated circuit device includes a digital filter, a voiced/unvoiced excitation circuit, a speech parameter interpolator, an input parameter decoder, a digital-to-analog converter, a speaker and associated timing circuits. A non-volatile memory stores digital data representative of the correct spellings of selected words in a foreign language and the model vocal tract control data necessary to control the speech synthesis circuit in a manner to cause the selected words to be audibly pronounced by the translator.

Electronic handheld translator having miniature electronic speech

A speech synthesis circuit is provided with a variable frame length data converter and the speech synthesizer is preferably integrated on an integrated circuit chips. The variable frame length data converter reduces the amount of data required to synthesizer human speech at a given quality level. Preferably, a full frame of data includes, a pitch parameter, an energy parameter, a repeat bit and a plurality of speech coefficients. Each parameter or coefficient has a preselected length, but each frame has a variable number of parameters or coefficients associated therewith. The parameters and coefficients are encoded and a particular code of the pitch parameter indicates that the speech is to be unvoiced. An unvoiced frame includes fewer coefficients that a voiced frame and the converter detects this particular pitch parameter and automatically sets the unsent coefficients to zero. The converter also detects the state of the repeat bit for controlling the synthesizing to use the coefficients received during the previous frame as the coefficient to be used to generate speech in response to the present frame. In this embodiment, when the repeat bit comes up, new pitch and energy parameters are inputted therewith. Further, the converters preferably detects particular codes in the energy parameter for determining when a pause occurs or when the last frame of data has been sent.

Variable frame length data converter for a speech synthesis circuit

This system includes an LPC parameter speech synthesizer which basically needs ten binary bits for each LPC coefficient. However, external sources are allowed reduced storage and frame rate requirements by encoding the set of LPC coefficients in a data frame with bit-allocation, repeat-bit, and variable-length features. A three-memory system provides transformation: a speech word selected by controller 11 is transformed by a ROM (30) into an address to a ROM (12 or 13) which outputs corresponding speech data in reduced encoded format to a ROM (202) which converts the coded frame of coefficients to uncoded ten-bit coefficients as needed by the speech synthesizer.

Speech synthesis system with parameter look up table

A method of designing and manufacturing a modular integrated circuit for a 4 bit microcomputer family utilizing a modular concept which is adaptable for a variety of applications and specific circuit desgins. The modular circuit is designed as a large block of cells which contains an ALU, instruction decoder, bus structure and a small amount of RAM and ROM as well as ROM control logic. In addition, the block contains attachment points for additional ROM and RAM and for special input/output devices such as I/O bus, timekeeping, A-D, D-A, display drive, communication ports and general purpose control lines.

Data processing system integrated circuit having modular memory add-on

An address decode scheme decodes address lines using a minimum number of electrical conductors and minimum area on the chip. Instead of decoding the true and the complementary signals of each address input using a PLA or static gate, the present decode scheme uses two sets of programmable transistors for respectively detecting zeros and ones on the address lines and for generating selected high and low decode signals in conjunction with precharge, discharge, and control transistors. This invention is equally effective in CMOS, NMOS, or PMOS technologies.

Address decode system

A system and method for driving a multiplexed liquid crystal display (LCD) of duty cycle 1/N is described. The drive system includes M number of segment conductors and N number of drive conductors arranged in a matrix array, the intersection of a drive conductor with a respective segment conductor representing one segment of the display. A signal generator is provided for generating first and second electrical signals having respective first and second predetermined frequencies, the second frequency being substantially greater than the first frequency. A first logic circuit applies the second signal to the drive conductors one-at-a-time in a predetermined sequence and applies the first signal during the remainder of the cycle. Similarly, a second logic circuit responsive to data signals indicative of the information to be displayed applies segment signals representing the ON/OFF states of each segment to the respective segment conductors. Each segment signal is comprised of a series of second signal components. The resultant signal applied to the ON segments has a higher frequency than that of the resultant signal applied to the OFF segments.

System and method of driving a multiplexed liquid crystal display by

A speech synthesis system utilizing a linear predictive filter. Voiced and unvoiced excitations are applied to the filter to produce a digital signal representative of human speech. The voiced excitation is provided by a repeating chirp function stored in memory. The unvoiced excitation consists of two excitation signals of opposite sign, stored in programmable memory and randomly addressed. The programmable storage of unvoiced excitation signals allows gain scaling between voiced and unvoiced excitation to be easily accomplished.

Method and apparatus for speech synthesis filter excitation

A system using a digital filter for generating complex waveforms, such as human speech. The filter has a multiplier, an adder coupled to the output of the multiplier and various delay circuits coupled to the output of the adder. A latch memory is coupled to the output of one of the delay circuits. Switching circuits are provided for the output of the delay and the latch memory to inputs of the multiplier and the adder to selected times. Coefficients of the filter are preferably stored in a memory coupled to another input of the multiplier. The excitation signal is coupled to the adder in one embodiment and to the multiplier in another embodiment.

System using digital filter for waveform or speech synthesis

A speech synthesis circuit capable of being implemented in an integrated circuit is disclosed. The speech synthesis circuit has an input port for receiving frames of data consisting of speech coefficients, a memory for storing interpolated values of the speech coefficients and an interpolator circuit coupled to the input port and to the memory. A synchronous timing circuit is provided for generating a data frame timing signal, interpolation count timing signals and parameter count timing signals. The rate of the parameter count timing signals is a multiple of the rate of the interpolation count timing signals, which is in turn a multiple of the rate of the data frame timing signal. These signals occur at predetermined times and are generated in the disclosed embodiment by Programmed Logic Arrays (PLA's). The data frame timing signal controls the receipt of a new frame of data at the input port. The interpolation count timing signal controls the initiation of a sequence of interpolations by the interpolator circuit between the values of the speech coefficients of the previous frame of data, and the values of the speech coefficients contained in the current frame. The parameter count timing signals are utilized to control when each coefficient is received at the input port after a data frame timing signal has occurred and also control the transferring of particular speech parameters to the interpolator circuit from the memory.

Synchronous method and apparatus for speech synthesis circuit

A system incorporating an integrated circuit device or chip which digitally synthesizes human speech using a linear predictive filter. The linear predictive filter comprises a single filter stage only which contains a single multiplier for selectively multiplying a plurality of coefficients, initiating the multiplication of one coefficient at a time, by using a feedback loop with multiplexing techniques so as to input multiplexed signals to the multiplier--as contrasted to a cascade of filter stages. Thus, the single multiplier of the linear predictive filter is utilized repetitively to provide the calculations required. The system also includes a memory for storage of digital filter coefficients, a controller for selectively accessing the coefficients, and a speaker for generating audible sounds.

Speech synthesis integrated circuit device

An integrated chip microprocessor system has a data memory for storing numeric data, an arithmetic unit for performing arithmetic operations on such data, an instruction memory for storing a plurality of instruction words, a program counter for addressing the instruction memory, and an instruction word decoder for decoding instruction words outputted from the instruction memory for controlling the operation of the microprocessor system. The instruction word decoder has a branch decoder system for implementing a two cycle branch logic. Each program branch operation, as stored in the instruction memory has two parts: a branch instruction word which indicates a program branch and also indicates the state of a selected one of a plurality of flag latches upon which it is conditioned; and a branch address instruction word solely indicative of the instruction memory address to which the program is to branch, the branch address instruction word being stored in the next memory location in the instruction memory following the branch instruction word. The branch decoder system determines when a branch instruction word is outputted from the instruction memory and also determines if the program branch is conditional or unconditional, and if the branch is conditional, the particular state of a selected flag latch upon which the branch is conditioned. If the branch is unconditioned, or if the branch is conditional and the condition satisfied, the branch decoder system inserts the branch address instruction word which is the next instruction word outputted from the instruction memory into the program counter.

Electronic microprocessor system having two cycle branch logic

A method of communicating Digital Speech Data to a speech synthesis circuit. The data is compressed to on the order of 1000-1200 bits, per second for normal human speech. The speech synthesis circuit utilizes linear predictive coding techniques for producing high quality speech or other sounds. The data is preferably stored in a memory which is coupled to the speech synthesis circuit. The data has variable frame lengths; in the disclosed embodiment, four different frame lengths are described having frame lengths from four bits to forty-nine bits. The memory stores the variable frame length data and communicates the same to the speech synthesis circuit in response to certain control signals.

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Lubbock, TX, United States of America

George L Brantingham