Psiquantum Corp.

Promos Technologies, Inc

George Kovall

Vimal Kumar Kamineni

Faraz Najafi

Syrus Ziai

Vitor Riseti Manfrinato

Chia-Jung Chung

Mark G Thompson

Jin-Ho Kim

Vei-Han Chan

Yong Liang

Chung Wai Leung

Chia-Shun Hsiao

Ching-Hwa Chen

Gabriel J Mendoza

Matteo Staffaroni

Zhong Dong

Chuck Jang

Chunchieh Huang

Kuei-Chang Tsai

Mark Thompson

Ann Melnichuk

Chunyuan Chao

Steven Ming Yang

Takashi Orimoto

Luu Nguyen

Himani Kamineni

A device includes a photonic integrated circuit (PIC) die and an electronic integrated circuit (EIC) die bonded to the PIC die. The PIC die includes a waveguide layer including a waveguide and a grating coupler configured to couple incident light into the waveguide, and a first set of dielectric layers on the waveguide layer. The EIC die includes a semiconductor substrate and a second set of dielectric layers on the semiconductor substrate. The first set of dielectric layers faces the second set of dielectric layers. The PIC die and the EIC die include a trench aligned with the grating coupler, the trench extending through the semiconductor substrate, the second set of dielectric layers, and the first set of dielectric layers to the waveguide layer such that the incident light may pass through the trench to reach the grating coupler. A multi-step dry etching process is used to form the trench.

Structure and method to remove semiconductor chip material for optical signal access to a photonic chip

A device includes a substrate, a dielectric layer on the substrate, a waveguide within the dielectric layer, and a photodetector optically coupled to the waveguide. The photodetector is disposed above the waveguide layer and is monolithically integrated with the substrate. The photodetector is configured to operate at low temperatures, such as below about 50 K or about 20 K. In some embodiments, the monolithic photonic device includes thermal isolation structures and optical isolation structures. Techniques for manufacturing the monolithic photonic device, including the thermal isolation structures and optical isolation structures, are also described.

Photonic integrated circuit

A superconductor device includes a barrier layer over a substrate including silicon, the barrier layer including silicon and nitrogen, and a seed layer for a superconductor layer over the barrier layer, the seed layer including aluminum and nitrogen, and superconductor layer over the seed layer, the superconductor layer including a layer of a superconductor material, the barrier layer serving as an oxidation barrier between the layer superconductor material and the substrate. In some embodiments, the superconductor device includes a waveguide and a metal contact at a sufficient distance from the waveguide to prevent optical coupling between the metal contact and the waveguide.

Superconducting nanowire single photon detector and method of fabrication thereof

A superconductor device is manufactured by depositing a barrier layer over a substrate including silicon, the barrier layer including silicon and nitrogen; depositing a seed layer for a superconductor layer over the barrier layer, the seed layer including aluminum and nitrogen; depositing the superconductor layer over the seed layer, the superconductor layer including a layer of a superconductor material, the barrier layer serving as an oxidation barrier between the layer superconductor material and the substrate; and depositing a silicon cap layer over the superconductor layer. In some embodiments, the superconductor device includes a waveguide and a metal contact at a sufficient distance from the waveguide to prevent optical coupling between the metal contact and the waveguide.

A superconductor device according to some embodiments comprises a superconductor stack, which includes a superconductor layer and a silicon cap layer over the superconductor layer, the cap layer including amorphous silicon. The superconductor device further comprises a metal contact over a portion of the silicon cap layer and electrically-coupled to the superconductor layer. The metal contact comprises a core including a first metal, and an outer layer around the core that includes a second metal. The portion of the silicon cap layer is converted from silicon to a conductive compound including the second metal to provide low-resistance electrical coupling between the superconductor layer and the metal contact. The superconductor device further comprises a waveguide, and the first portion of the cap layer under the metal contact is at a sufficient lateral distance from the waveguide to prevent optical coupling between the metal contact and the waveguide.

Conventional fabrication of sidewall oxide around an ONO-type memory cell stack usually produces Bird's Beak because prior to the fabrication, there is an exposed sidewall of the ONO-type memory cell stack that exposes side parts of a plurality of material layers respectively composed of different materials. Certain materials in the stack such as silicon nitrides are more difficult to oxidize than other materials in the stack such polysilicon. As a result oxidation does not proceed uniformly along the multi-layered height of the sidewall. The present disclosure shows how radical-based fabrication of sidewall dielectric can help to reduce the Bird's Beak formation. More specifically, it is indicated that short-lived oxidizing agents (e.g., atomic oxygen) are able to better oxidize difficult to oxidize materials such as silicon nitride and the it is indicated that the short-lived oxidizing agents alternatively or additionally do not diffuse as deeply through already oxidized layers of the sidewall such as silicon oxide layers. As a result, a more uniform sidewall dielectric can be fabricated with more uniform breakdown voltages along it height.

Method of forming ONO-type sidewall with reduced bird's beak

Inwardly-tapered openings are created in an Anti-Reflection Coating layer (ARC layer) provided beneath a patterned photoresist layer. The smaller, bottom width dimensions of the inwardly-tapered openings are used for defining further openings in an interlayer dielectric region (ILD) provided beneath the ARC layer. In one embodiment, the ILD separates an active layers set of an integrated circuit from its first major interconnect layer. Further in one embodiment, a taper-inducing etch recipe is used to create the inwardly-tapered ARC openings, where the etch recipe uses a mixture of CF4 and CHF3 and where the CF4/CHF3 volumetric inflow ratio is substantially less than 5 to 1, and more preferably closer to 1 to 1.

Dynamically controllable reduction of vertical contact diameter through adjustment of etch mask stack for dielectric etch

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Campbell, CA, United States of America

George Kovall