Apple Inc.

P.a. Semi, Inc.

Broadcom Corporation

George Kong Yiu

Ruchi Wadhawan

James B Keller

Sridhar Subramanian

Ramesh B Gunna

Jason M Kassoff

Mark Pearce

Sridhar P Subramanian

In one embodiment, a cache comprises a data memory comprising a plurality of data entries, each data entry having capacity to store a cache block of data, and a cache control unit coupled to the data memory. The cache control unit is configured to dynamically allocate a given data entry in the data memory to store a cache block being cached or to store data that is not being cache but is being staged for retransmission on an interface to which the cache is coupled.

Cache used both as cache and staging buffer

In one embodiment, a switch is configured to be coupled to an interconnect. The switch comprises a plurality of storage locations and an arbiter control circuit coupled to the plurality of storage locations. The plurality of storage locations are configured to store a plurality of requests transmitted by a plurality of agents. The arbiter control circuit is configured to arbitrate among the plurality of requests stored in the plurality of storage locations. A selected request is the winner of the arbitration, and the switch is configured to transmit the selected request from one of the plurality of storage locations onto the interconnect. In another embodiment, a system comprises a plurality of agents, an interconnect, and the switch coupled to the plurality of agents and the interconnect. In another embodiment, a method is contemplated.

Non-blocking address switch with shallow per agent queues

In various embodiments, an apparatus comprises a plurality of agents and an interconnect. In one embodiment, the plurality of agents includes first through fourth agents. The interconnect comprises a plurality of segments that are switchable (e.g. using a plurality of selection circuits) to form communication paths between the agents, and a first segment is included in a first communication path from the first agent to the second agent, and is also included in a second communication path from the third agent to the fourth agent. In another embodiment, each segment is driven by a selection circuit. At least one selection circuit has at least one segment and an output from at least one agent as inputs. In yet another embodiment, an arbiter is configured to determine a communication path on the interconnect for each requesting agent to the destination agent over the segments. The arbiter is configured to arbitrate among a subset of requests for which each segment in the corresponding communication path is available.

Segmented interconnect for connecting multiple agents in a system

A CAM may include a plurality of CAM cells. Each CAM cell is configured to generate an output indicating if a corresponding input bit and the bit stored in that CAM cell match. A circuit is configured to logically AND the outputs to generate a hit output. A first compare line generator circuit is configured to generate a first pulse responsive to a clock signal and a data signal and a second compare line generator circuit is configured to generate a second pulse responsive to the clock signal and the complement of the data signal. A CAM may include a circuit configured to generate a pulse indicating a hit in an entry of the CAM and a latch circuit configured to capture the pulse responsive to the first clock signal and configured to clear responsive to the second clock signal. A first CAM may store a value in each entry and may further store a compare result. A second CAM may include entries corresponding to the entries in the first CAM, and each entry may be coupled to receive the indication of the compare result from the corresponding entry of the first CAM and is configured to generate a second compare result which includes the first compare result.

Growing community of inventors

Sunnyvale, CA, United States of America

George Kong Yiu