Gte Communication Systems Corporation

Gte Automatic Electric Incorporated

Gte Automatic Electric Labs Inc.

George K Tarleton

Robert J Abrant

Michael D Martys

An address generator which provides addresses for machine storage and software retrieval of computer status information. A counter is used to generate address signals in a descending order until it is disabled by a computer during alarm conditions. Under such conditions the counter provides a bias address for referencing the most recent status word. A gating circuit gates computer generated address signals to an adder circuit during the alarm conditions. The adder circuit adds the computer generated address signals to the counter generated bias signal to provide address signals which reference physical storage locations in a memory.

Address generator

A synchronizing circuit that synchronizes the non-maskable interrupt (NMI) input signals of two separate microprocessor subsystems that are running synchronously as part of a fault tolerant computer system. This circuit enables both microprocessors to detect and respond to an error condition at an identical point in their relative bus timing sequence even though there may be a real time skew between the bus timing of these two subsystems. Storage and gating circuitry are used to provide the precise timing signals required for such synchronization.

Interrupt synchronizing circuit

A synchronizing circuit synchronizes the asynchronous ready signals for two separate microprocessor subsystems that are running synchronously as part of a fault tolerant computer system. Duplicated synchronization circuits, confined in a master-slave arrangement, are utilized with the duplicate microprocessors. Storage and gating circuitry are used to provide the precise timing signals required for such synchronization.

Ready line synchronization circuit for use in a duplicated computer

A circuit which eliminates race conditions caused by gate delay variation. In the absence of gate delay variations data is made available for a period of time which extends beyond commencement of processing of such data. This circuit prevents gate delay variations from causing processing to commence after the period of time during which data is available. Each of a pair of flip-flops initiates or terminates the data available time period. These flip-flops, an exclusive-or gate and related circuitry are arranged such that the period of time for data availability is not terminated until after processing of such data actually commences.

Race condition mediator circuit

A low voltage protection which prevents an associated circuit from generating erroneous signals during power-up, power-down or power failure conditions. A voltage comparison circuit, powered by a first power supply, detects low voltage conditions in a second power supply and causes a switching circuit to inhibit control and power signals of the associated circuit.

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Itasca, IL, United States of America

George K Tarleton