Western Digital Technologies, Inc.

Western Digital Corporation

Other

Wangdat, Inc.

George J Bennett

Robert P Ryan

Steven R Vasquez

Charles Royston Patton, Iii

Raffi Codilian

Dean Mitcham Jenkins

Orhan Beker

Aswartha Narayana

Donald George Stupeck

Robert D Catiller

Some embodiments of the invention are directed to a data storage system that includes a disk and solid-state non-volatile memory (NVM). During a power failure, the data storage system may use back EMF (BEMF) voltage from the spindle motor of the disk to park the heads of the disk and/or store data in the NVM. In one embodiment, a demand regulation circuit regulates loads that use voltage generated from the BEMF. The demand regulation circuit may be used to selectively cause a controller to adjust the rate of programming to the NVM in order to reduce the load. For example, the demand regulation circuit may assert a throttle signal to the controller upon detecting that the voltage generated from the BEMF is below a certain threshold. Programming rate may be throttled, programming cycles may be staggered, and/or programming time may be lengthened. Throttling may enable the use of smaller circuitry.

Systems and methods for data throttling during disk drive power down

A switching voltage regulator is disclosed including a charging element operable to generate an output voltage. The charging element is configured during a cycle, including to charge the charging element for an on-time, discharge the charging element for a discharge time, and tristate the charging element for a tristate time. Prior to a power mode changing which increases the current demand of the load, the on-time is increased.

Switching voltage regulator employing current pre-adjust based on power mode

An oscillator is disclosed comprising a first crystal operable to generate a first oscillating signal at a first frequency, and a second crystal coupled to the first crystal and operable to generate a second oscillating signal at a second frequency higher than the first frequency. The oscillator further comprises a DC restore circuit operable to generate a third oscillating signal comprising a substantially fifty percent duty cycle in response to the second oscillating signal.

Dual frequency crystal oscillator

An analog-to-digital converter is disclosed comprising a resonant oscillator comprising an input operable to receive an analog input signal and an output operable to output an oscillating signal. A DC offset detector detects a DC offset in the oscillating signal caused by the analog input signal, wherein the DC offset is converted into a digital output signal representing the analog input signal.

Analog-to-digital converter with input voltage biasing DC level of resonant oscillator

An analog-to-digital converter (ADC) is disclosed operable to convert a sensor signal to a digital value. A differential amplifier responsive to the sensor signal and a reference signal generates a first analog signal representing a first offset above the reference signal and a second analog signal representing a second offset below the reference signal. A first oscillator generates a first output frequency dependent on the first analog signal, and a second oscillator generates a second output frequency dependent on the second analog signal. A difference between the first output frequency and the second output frequency is generated, and the digital value representing the sensor signal is generated in response to the difference.

Analog-to-digital converter comprising dual oscillators for linearity compensation

A computing device is disclosed comprising digital circuitry, and a gate speed regulator operable to generate a supply voltage applied to the digital circuitry. A frequency synthesizer generates a first reference frequency, and a propagation delay oscillator generates a first oscillation frequency in response to the supply voltage, wherein the first oscillation frequency is compared to the first reference frequency to generate a first error signal. A reference oscillator generates a second reference frequency in response to a reference voltage, and a startup oscillator generates a second oscillation frequency in response to the supply voltage, wherein the second oscillation frequency is compared to the second reference frequency to generate a second error signal. An adjustable circuit, responsive to the first and second error signals, adjusts the supply voltage applied to the digital circuitry.

Ensuring minimum gate speed during startup of gate speed regulator

A computing device is disclosed comprising digital circuitry including a critical path circuit, and a gate speed regulator. A ring oscillator generates an oscillation frequency, and dither circuitry periodically adjusts a number of inverter elements in the ring oscillator in order to adjust an average propagation delay of the ring oscillator relative to a propagation delay of the critical path circuit. A comparator compares the oscillation frequency to a reference frequency to generate an error signal, and an adjustable circuit, responsive to the error signal, adjusts at least one of a supply voltage and a clocking frequency applied to the digital circuitry.

Gate speed regulator dithering ring oscillator to match critical path circuit

A computing device is disclosed comprising digital circuitry fabricated on a multi-layer integrated circuit including a first layer and a second layer, and a multi-layer ring oscillator operable to generate a propagation delay frequency representing a propagation delay of the integrated circuit, wherein the multi-layer ring oscillator comprises a first interconnect fabricated on the first layer and a second interconnect fabricated on the second layer. The propagation delay frequency is compared to a reference frequency to generate a frequency error, and at least one of a supply voltage and a clocking frequency applied to the digital circuitry is adjusted in response to the frequency error.

Regulating power consumption of digital circuitry using a multi-layer ring oscillator

A disk drive comprising a disk, a head actuated over the disk, a read/write channel, a control processor, and a servo system is disclosed. The servo system is configured to read servo information from a servo wedge on the disk via the read/write channel, to generate first and second status information based on the read servo information, to output the first and second status information to the control processor, and to output first and second interrupt signals to the control processor, the first and second interrupt signals being spaced apart by a time delay. In response to the first interrupt signal, the control processor is configured to determine whether to release data from a host based on the first status information, and in response to the second interrupt signal, the control processor is configured to determine whether to release data from the host based on the second status information.

Methods and systems for fast release of data from a host by a disk drive

A disk drive is disclosed comprising a disk having a plurality of tracks, wherein each track comprises a plurality of data sectors. The disk drive further comprises a head actuated over the disk, and control circuitry fabricated on a die. A plurality of disk access commands are received from a host and stored in a command queue, wherein each disk access command identifies at least one data sector. A temperature of the die is determined, and a first disk access command is selected from the command queue in response to the die temperature.

Disk drive adjusting command execution in response to control circuitry die temperature

A switching voltage regulator is disclosed operable to regulate a voltage supplied to system circuitry. A comparator compares an oscillator signal generated by a ring oscillator to a reference signal generated by a frequency generator. Switching circuitry charges a charging element in response to the comparison, and control circuitry adjusts a number of delay elements in the ring oscillator and a divider value of the frequency generator to generate hysteresis in the comparison. In one embodiment, the charging element is charged while a frequency of the reference signal is above a frequency of the oscillator signal.

Switching voltage regulator employing dynamic voltage scaling with hysteretic comparator

A disk drive is disclosed comprising a head actuated over a disk having a plurality of data tracks and a first and second set of reserved tracks, wherein the first set of reserved tracks are located at a first radial location, and the second set of reserved tracks are located at a second radial location different than the first radial location. A write command is received from a host, wherein the write command comprises user data which is stored in a cache memory. When a power failure is detected, whether the head is nearer to the first or second set of reserved tracks is determined, and then the head is positioned to the nearest of the first and second set of reserved tracks. The user data stored in the cache memory is written to the reserved tracks, and the head is unloaded onto a ramp.

Disk drive flushing write cache to a nearest set of reserved tracks during a power failure

A disk drive is disclosed including a disk having a plurality of servo tracks. The servo tracks are banded together to form a plurality of servo track bands, and each servo sector comprises a fine track address that identifies one of the servo tracks. The disk drive further comprises a head attached to a distal end of an actuator arm operable to generate a read signal by reading the disk, and a mechanical position sensor operable to detect a coarse position of the actuator arm. The coarse position is processed to identify one of the servo track bands, and the read signal is processed to detect one of the fine track addresses, wherein the detected fine track address identifies a servo track within the identified servo track band. The identified servo track band is combined with the detected fine track address to generate a servo track address.

Disk drive employing coarse position feedback from mechanical position sensor to improve format efficiency

Control circuitry is disclosed including an oscillator operable to generate an oscillator signal. A frequency of the oscillator signal increases as an amplitude of a first voltage increases up to a threshold, and the frequency of the oscillator signal decreases as an amplitude of the first voltage exceeds the threshold. The oscillator is operable to generate a foldover signal indicating when the frequency of the oscillator signal is decreasing due to the first voltage exceeding the threshold.

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Murrieta, CA, United States of America

George J Bennett