International Business Machines Corporation

George Henry Thiel

Sanjeev Balwant Sathe

David V Caletka

Randall Joseph Stutzman

Donald W Henderson

Krishna Darbha

Lawrence P Lehman

Voya Rista Markovich

Kishor V Desai

William Infantolino

Timothy F Carden

Stephen R Engle

Glenn O Dearing

William Louis Brodsky

David L Questad

Donna Jean Trevitt

Tien Y Wu

Patrick Robert Zippetelli

Anne Marie Quinn

Bruce John Chamberlin

Mitchell G Ferrill

Solder balls, such as, low melt C4 solder balls undergo volume expansion during reflow. Where the solder balls are encapsulated, expansion pressure can cause damage to device integrity. A volume expansion region in the semiconductor chip substrate beneath each of the solder balls accommodates volume expansion. Air-cushioned diaphgrams, deformable materials and non-wettable surfaces may be used to permit return of the solder during cooling to its original site. A porous medium with voids sufficient to accommodate expansion may also be used.

Method to accommodate increase in volume expansion during solder reflow

Solder balls such as, low melt C4 solder balls, undergo volume expansion during reflow, such as may occur during attachment of chip modules to a PCB. Where the solder balls are encapsulated, expansion pressure can cause damage to device integrity. A volume expansion region in the semiconductor chip substrate beneath each of the solder balls accommodated this volume expansion. Air-cushioned diaphgrams, deformable materials and non-wettable surfaces may be used to permit return of the solder during cooling to its original site. A porous medium with voids sufficient to accommodate expansion may also be used.

Method of accommodating in volume expansion during solder reflow

A method of self-healing cracks in a cured epoxy base underfill material between an I/C chip and a substrate is provided. A plurality of capsules is dispersed in the epoxy base. Each capsule has a curable thermosetting adhesive encapsulated in a rupturable shell to disperse the thermosetting adhesive in a crack in the epoxy base when the shell ruptures. Each capsule is less than 25 microns in diameter. A curing agent that will cause a reaction of the thermosetting adhesive on contact is dispersed in the epoxy to form a cured adhesive in a crack in said epoxy base. The shell will rupture when encountering a crack being propagated in the underfill material, which will at least partially fill the crack with the adhesive, and cure the adhesive with the curing agent to bond the edges of the crack together. The invention also includes the structure for crack self-healing.

Method and structure for self healing cracks in underfill material between an I/C chip and a substrate bonded together with solder balls

A semiconductor chip package having a non-planar chip therein, to reduce the stress concentrations between the chip and cover plate. In particular, a chip and method of forming a chip having a non-planar or 'domed' back surface, wherein the thickness of the non-planar chip is greatest substantially near the center of the chip. Further, a method of rounding the edges or corners of the chip to reduce crack propagation originating at the edges of the chip.

Non-planar surface for semiconductor chips

A semiconductor chip module and forming method is provided. The module includes a support member having at least one well being open to receive a semiconductor chip. Each well depth is substantially equal to the thickness of a chip. The support member has a planar region surrounding each well. A chip is in each well. A dielectric sheet of material is laminated over each chip and extends onto the planar area surrounding the wells and has a face oriented away from the chip. Electrical circuitry including capture pads is formed on the face of the dielectric sheet and extends onto the sheet that overlies the planar region. Conducting vias are formed in the dielectric sheet connecting the electrical circuitry on the dielectric sheet with the contact pads on the chip. A multilayer, circuitized laminate having a fan-out pattern is laminated to the dielectric sheet.

Wafer with semiconductor chips mounted thereon

Semiconductor chip module and method of manufacture of same

A semiconductor chip package having a non-planar chip therein, to reduce the stress concentrations between the chip and cover plate. In particular, a chip and method of forming a chip having a non-planar or &ldquo;domed&rdquo; back surface, wherein the thickness of the non-planar chip is greatest substantially near the center of the chip. Further, a method of rounding the edges or corners of the chip to reduce crack propagation originating at the edges of the chip.

Structure to accommodate increase in volume expansion during solder reflow

A chip carrier package that includes a cover plate attached to the stiffener by a reflowable bonding material is disclosed. Additionally, a thermally and electrically conductive bonding material between the cover plate and the chip itself may be included. Also a chip package including an alignment device to aid in properly aligning the cover plate on the stiffener is disclosed. Furthermore, a method of packaging a chip including providing a reflowable material between the cover plate and stiffener body for attaching the cover plate to the stiffener, and simultaneously attaching the cover plate to the stiffener with an attaching of the carrier to an electronic circuit board is disclosed.

Method of packaging a high performance chip

An electronic package is provided including a substrate, a device mounted on the substrate, and a solder member electrically coupling the device to the substrate. The package includes a dielectric material positioned substantially around the solder member which forms a physical connection between the substrate and the device. The volume of the solder member contracts during melting thereof to prevent failure of the physical connection and/or the electrical coupling between the substrate and the device.

Negative volume expansion lead-free electrical connection

A chip carrier package that includes a cover plate attached to the stiffener by a reflowable bonding material is disclosed. Additionally, a thermally and electrically conductive bonding material between the cover plate and the chip itself may be included. Also a chip package including an alignment device to aid in properly aligning the cover plate on the stiffener. Furthermore, a method of packaging a chip including providing a reflowable material between the cover plate and stiffener body for attaching the cover plate to the stiffener, and simultaneously attaching the cover plate to the stiffener with an attaching of the carrier to an electronic circuit board.

High performance chip packaging and method

A multi-layer printed circuit board including at least one layer of an electrically conducting material and at least one layer of an electrically insulating material. At least one through hole formed at least through the at least one layer of electrically conducting material. The at least one through hole includes a material plated on an interior surface thereof. At least one thermal break is provided in the at least one layer of electrically conducting material, such that heat passing between the through hole and the at least one layer of electrically conducting material passes through the at least one thermal break. At least one electrical connection provided in the at least one layer of electrically conducting material between the material plated on the interior surface of the through hole and the at least one layer of electrically conducting material. At least a portion of the at least one electrical connection is between the through hole and the at least one thermal break.

Thermal/electrical break for printed circuit boards

The bond strength between a semiconductor chip and a metal heat sink in an integrated circuit package can be improved by using an adhesive system comprising two separate layers, one layer exhibiting preferential bonding strength for the chip and the other layer exhibiting preferential bonding strength for the metal heat sink.

Growing community of inventors

Endicott, NY, United States of America

George Henry Thiel