Teletype Corporation

George Heckel

Gary B Ollendick

A cache memory 30 having a thirteen bit word length is illustrated for storing more than one data word read from a system memory 80 having an eight bit word length and providing the stored words to a video display 18 on a reoccurring basis. The cache memory 30 has a storage capacity sufficient to store the words for one row of display text characters. Two system memory bytes are concatenated by a latch 74 and storage buffer 96 prior to writing into the cache memory 30. After the scanning of the first word of the last scan line in the current cathode ray tube (19) display text row, the first word of the new text row is written into the cache memory (30) from the system memory (80). The write procedure is completed before the last word of the new text row is read from the cache memory 30 to the cathode ray tube display 19 during the writing of the first scan line of the new text row.

Cache memory and control circuit

A re-entrant shift register comprising eight levels and in the illustrative embodiment eight stages per level, is selectively used in the buffering of information between an asynchronous signal source, e.g., a manual keyboard and a data sink, e.g., a controller which accepts information upon an asynchronous basis. Information to be transmitted from a data source to the data sink is entered in parallel in a register in the form of a latch under control of write control circuitry. Similarly, data to be transmitted to the asynchronous data sink is temporarily stored in a parallel output register in the form of a latch. The writing of information into and out of the output latch is under the control of read control circuitry. The write control circuit includes a write counter and the read control circuit includes a read counter. These counters are advanced by a common clock signal which is further utilized in the gating of information within the write control and read control circuits and in the control of the shift register. The shift register and the attendant input and output circuitry is arranged such that an information word can be selectively routed directly between the input latch and the output latch to eliminate the delay incurred in traversing the shift register whenever the input and output data rates are such that buffering is not required. Additionally, where the input information indicates that an input data word is being repeated, the information is gated directly from the input latch to the output latch independently of the rate at which the input signals occur.

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Mundelein, IL, United States of America

George Heckel