Xilinx, Inc.

Other

Signetics

George H Simmons

Kameswara K Rao

Wei-Yi Ku

Anders T Dejenfelt

David Chiang

Derek R Curd

Napoleon W Lee

Sholeh Diba

Thomas Y Ho

Robert W Barker

Tomoyuki Furuhata

A two-transistor flash EPROM cell for high-speed high-density PLD applications is provided. The two-transistor cell includes a storage transistor connected in series to an access transistor. The storage transistor prevents problems associated with both over-erase and punch-through, and allows for scaling of the gate length to realize 5V cell programming.

Method of forming a two transistor flash EPROM cell

Two transistor flash EPROM cell

A wordline driver for a wordline in an integrated programmable logic device (PLD) having flash memory cells. The wordline driver includes an input terminal that accepts a binary wordline input signal, a pass gate coupled to the input terminal and to a mode-control terminal, and an inverter that receives an input from the pass gate or the mode-control terminal, depending on the operating mode of the PLD. The output signal from the inverter is coupled to a multiplexer that selects between that output and a signal from a voltage supply, the signal selected depending on the operating mode of the PLD. The multiplexer outputs the selected signal to the wordline of the PLD.

Wordline driver for flash PLD

More than one security bit is used in a block of a PLD chip. The internal configuration and other information is left unprotected when all the security bits are in the erased state, and is protected by programming one or all the security bits. The security bits are located physically in proximity to the areas containing configuration and any other user-defined data, both so that they are difficult to discover and so that the erasure of all security bits in a EPROM-based PLD would cause a large number of adjacent user-defined bits to be erased as well, hence making it very difficult to extract useful information from a protected device by reverse engineering. Situating security bits in a different, pseudorandom location within each block of the chip makes them difficult to find and so further inhibits reverse engineering.

Programmable logic device having security elements located amongst

A break-away coupling for mounting an elongated member, such as a roadside sign post, includes two opposingly fixed engagement members connected to one another end-to-end. The first engagement member is attached relative to the ground either by a plate or by a plate attached to a stake-like member. The second engagement member is attached to the elongated member. The engagement members have facing flange plates, each flange plate having an opening aligned with an opening in the other plate and a shear bolt projects through the openings to fix the flanges plates together. The shear bolt is either constructed of relatively easy-to-break material or includes a weakened area. When the elongated member is struck, the shear bolt breaks and the engagement members disconnect without damage. The bolt is easily replaced to quickly reassemble the sign post.

Break-away coupling

A CMOS, N-well, P-channel static RAM cell with merged bipolar transistors as its output drivers.

CMOS RAM with merged bipolar transistor

This invention relates to a unique, improved, inexpensive, one-piece garment or equipment hanger which can be securely attached to the diagonal rod or wire, of which the common chain link type fence is constructed; and this hanger can be formed of such size and shape that it may be inserted along with the tennis balls at the ball packaging facility.

Growing community of inventors

Sunnyvale, CA, United States of America

George H Simmons