Digital Equipment Corporation

George H Lord

John Kirk

Kim A Meinerth

A duplicate cache tag store, accessible to a graphics processor and to devices connected to the I/O bus without creating traffic on the system bus. Any entry into, or displacement from, the CPU cache tag store is also entered into, or displaced from, the second cache tag store. The disclosure further describes a computer graphics system, having a graphics processor capable of reading from or writing to main memory, including virtual memory, without any action by the CPU; having a FIFO command buffer in main memory for temporary storage of graphics commands; having a residue buffer for the temporary storage of memory transmissions not immediately usable by the graphics processor; having a 'short circuit' feature for routing graphics commands to the command processor in the minimum number of steps; having a cursor control system capable of storing cursor pattern information in, and retrieving cursor pattern information from, main memory; having a cursor bus that is reconfigurable to carry information other than cursor information; and having a frame buffer module that contains no timing or cursor control circuitry.

Duplicate cache tag store for computer graphics system

A computer workstation including a processor, one or more input/output units, such as disk devices or network interfaces, a program memory and a video memory which contains video information displayed on a video monitor. An arbitration circuit selects among the processor and input/output units for transfers to and from the program memory and video memory. A master control circuit controls timing of transfers to and from the program and video memories, and periodically enables video update transfers of video information from the video memory to video control circuits, which control the video monitor. While a video update is in progress, the master control circuit holds off other transfer request of the processor and input/output units with the memory. The program memory stores interrupt vectors. In response to interrupt requests from units which require interrupt service, the master control circuit interrupts the processor. When the processor acknowledges the interrupt, the master control circuit enables the transfer from the memory to the processor of the interrupt vector associated with the highest priority interrupt.

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Stow, MA, United States of America

George H Lord