Infinite Technology Corp.

Advanced Micro Devices Corporation

George H Landers

Om P Agrawal

Jerry D Moench

Kerry A Ilgenstein

Nicholas A Schmitz

Earle W Jennings, Iii

Earle Jennings

Glen Haas

Tim B Smith

A reconfigurable processor includes at least three (3) MacroSequencers (,)-(,) which are configured in an array. Each of the MacroSequencers is operable to receive on a separate one of four buses (,) an input from the other three MacroSequencers and from itself in a feedback manner. In addition, a control bus (,) is operable to provide control signals to all of the MacroSequencers for the purpose of controlling the instruction sequence associated therewith and also for inputting instructions thereto. Each of the MacroSequencers includes a plurality of executable units having inputs and outputs and each for providing an associated execution algorithm. The outputs of the execution units are input to an output selector which selects the outputs for outputs on at least one external output and on at least one feedback path. An input selector (,) is provided having an input for receiving at least one external output and at least the feedback path. These are selected between for input to select ones of the execution units. An instruction memory (,) contains an instruction word that is operable to control configurations of the datapath through the execution units for a given instruction cycle. This instruction word can be retrieved from the instruction memory (,), the stored instructions therein sequenced through to change the configuration of the datapath for subsequent instruction cycles.

Processor with reconfigurable arithmetic data path

Each programmable logic device in at least two families of high density segmented programmable array logic device utilizes a programmable switch interconnection matrix to couple an array of symmetric programmable logic blocks. Each programmable logic block includes programmable logic macrocells, programmable input/output macrocells, a logic allocator and a programmable product term array. The programmable switch matrix provides centralized global routing with a fixed path independent delay and decouples the logic macrocells from the product term array. The logic allocator decouples the product term array from the logic macrocells, and the I/O macrocells decouple the logic macrocells from the package I/O pins. The logic allocator steers product terms from the product term array to selected logic macrocells so that no product terms are permanently allocated to a specific logic macrocell. In a first PLD of each family, a first predetermined number of input lines couple the switch matrix to each programmable logic block. In a second PLD of each family, a second predetermined number of input lines couple the switch matrix to each programmable logic block. The number of input lines to each programmable logic block and to the switch matrix are selected to provide a predetermined routability factor. The second family of PLDs has a larger pin to logic ratio than the first family of PLDs.

High density programmable logic device

A programmable logic device (PLD) and configurable logic network in which one or more logic combination networks (LCN) each receives logic inputs from two or more PLDs (PLD1, PLD2) and generates logic outputs (O, P) which provide inputs to programmable selectors (POR, UCL, . . . ) for controlling implementation of logic functions of various types and functionality by a controllable logic function sub-network by routing through the sub-network, logic values and logic instructions originating externally of the PLD's. Each programmable logic device includes an AND logic array (FAND . . . ) having inputs for receiving signals (Ax, Bx) and generating product term output signals and an OR logic array (OG . . . ) having inputs for receiving signals and generating sum term output signals (OF . . . ). One or both of the AND logic and OR logic arrays is programmable and the logic arrays are interconnected to apply output signals from one of them as input signals to the other one, the output from which provides PLD output signals. The logic combination networks may be fixed logic networks (LCN100) or programmable logic function generators (UBLFG2O, UBFF2P) that produce outputs controlled by a set of programmable inputs (CNx, DNx) to the generator as a function of the logic inputs (O,P) received from the programmable logic devices.

Configurable logic networks

A programmable logic device includes groups of AND logic function gates, the AND logic function gates in each group coupled to a logic OR function output gate associated with that AND logic function gate group. Each AND logic function gate group includes an output AND logic function gate having inputs that are programmable by respective programmable logic function generators (PLFG) of a set of PLFGs operatively associated with that output AND logic function gate. The PLFGs in any set of PLFGs receive the same sets of first logic input groups, and second programmable inputs. Operation of Boolean function generator output stages to carry out logic operations is controlled by first inputs from the logic OR function gates, and second programmable inputs received from logic cells according to logic inputs to said programmable cells. Inputs from the logic OR function gates are selected by programmable OR logic function generators. The PLFGs and BLFGs comprisise logic circuitry to generate output signals determined by any logic function of a plurality of the first logic inputs, and the second inputs. Using this PLD structure, outputs from the PLD can be used to control logic operations performed by the BLFGs using logic values and instructions originating externally of the PLD.

Programmable logic device

A logic system comprising one or more logic networks that can perform a variety of preconfigured or preconfiguarable logic functions. Each logic network is functionally separate from but operatively associated with one or more programmable circuits from which the logic network receives various logic signals. A first logic signal selects or preconfigures the desired logic function to be performed by the or each logic network while a second logic signal controls the operation of the selected logical function. The first logic signal can select a particular logic function to be performed by the logic network based on the contents of programmable cells in the network that are separate from the programmable circuits that supply the logic signals. Alternatively, the first logic signals can switch between various sub-networks each dedicated to performance of a preconfigured logic function. In this manner, the programmable circuit can essentially be dedicated to selecting which of various predetermined logic functions is to be utilized and is relieved of significant functional overhead associated with data manipulation. This can permit a smaller size programmable logic, gate or memory array to be used to control a logic operation of a given complexity, or a given size of array to control more complex operations. Both the programmable circuit(s) and the logic network(s) can be integrated in a single semiconductor chip.

Logic system of logic networks with programmable selected functions and

Family of multiple segmented programmable logic blocks interconnected by

A high density segmented programmable array logic device utilizes a programmable switch interconnection matrix to couple an array of symmetric programmable logic blocks. Each programmable logic block includes programmable logic macrocells, programmable input/output macrocells, a logic allocator and a programmable product term array. Further, the switch matrix provides centralized global routing with a fixed path independent delay. The programmable switch interconnection matrix decouples the logic macrocells from the product term array. The logic allocator decouples the product term array from the logic macrocells, and the I/O marcrocells decouple the logic macrocells from the package I/O pins. Thus, the architecture of this invention is easily scalable to higher density devices without compromising speed. The logic allocator steers product terms from the product term array to selected logic macrocells so that no product terms are permanently allocated to a specific logic macrocell.

Growing community of inventors

Mountain View, CA, United States of America

George H Landers