Motorola Corporation

George F Carney

Douglas G Mitchell

Francis J Carney, Jr

Cary B Powell

Francis J Carney

James H Knapp

Addi B Mistry

Timothy Lee Johnson

Eric J Woolsey

Joseph English

Kandis Mae Knoblauch

David Austin

Scott K Pozder

Vijay Sarihan

Deborah A Hagen

Marion I Simmons

James H Kleffner

Rina Chowdhury

Rebecca G Cole

Kartik Ananthanarayanan

A method of manufacturing a semiconductor component includes depositing a first electrically conductive layer ( ) over a substrate ( ), forming a patterned plating mask ( ) over the first electrically conductive layer, coupling a first plating electrode ( ) to the first electrically conductive layer without puncturing the plating mask, and plating a second electrically conductive layer onto portions of the first electrically conductive layer. A plating tool for the manufacturing method includes an inner weir ( ) located within an outer weir ( ), an elastic member ( ) over a rim ( ) of the outer weir, a pressure ring ( ) located over the rim of the outer weir and the elastic member, and a plurality of cathode contacts ( ) located between the pressure ring and the outer weir. The substrate is positioned between the elastic member and the pressure ring.

Method of manufacturing a semiconductor component

A method of manufacturing electronic components includes disposing a top metal layer ( ) comprised of solder over a bottom metal layer ( ) comprised of titanium or tungsten, and selectively etching the bottom metal layer ( ) over the top metal layer ( ) with an etchant mixture ( ) comprised of an etchant, an additive to control the temperature of the etchant mixture ( ), and another additive to reduce the redeposition of the top layer ( ).

Method of manufacturing electronic components

An interconnect structure, such as a flip-chip structure, including a base pad and a stud formed on the base pad and extending from the base pad is disclosed. The stud and base pad are formed to be continuous and of substantially the same electrically conductive base material. Typically, a solder structure is formed on the stud wherein the solder structure is exposed for subsequent reflow attachment to another structure. The present invention relates to packaging integrated circuits, more particularly to the structure and processing of a stud and bump without the standard under bump metallurgy.

Method and apparatus for manufacturing an interconnect structure

Method of manufacturing a semiconductor component and plating tool therefor

A semiconductor device (10) includes a bump structure that reduces stress and thus reduces passivation cracking and silicon cratering that can be a failure mode in semiconductor manufacturing. The stress is reduced by forming a polyimide layer (16) over a passivation layer (14). The polyimide layer (16) is extended beyond an edge of the passivation layer (14) over the metal pad (12). A solder bump (22) is composed of a eutectic material and is formed on the metal pad (12) and on the polyimide layer (16). The polyimide layer (16) prevents the solder bump (22) from contacting the passivation layer (14). This is useful for electroless or electroplating technology and may also be useful in other types of bump forming technology such as C4 and E3.

Method and apparatus for stress relief in solder bump formation on a

A method for forming an electrical interconnect on a substrate. At least one pad (14) is formed on a substrate (11). The pad (14) is formed having a non-wetting surface (12) and a wettable surface (13). Photoresist (44) is patterned on a substrate (41) forming a cavity on a pad (46) leaving a non-wetting surface (42) and a wettable surface (43) exposed. Interconnect material (56) is formed on a non-wetting surface (52) and a wettable surface (53) of pad 57. Interconnect material (56) is reflowed forming an interconnect ball (74) on a wettable surface (73). Surface tension causes interconnect material (56) when reflowed to flow from a non-wetting surface (72) to the wettable surface (73) and ball up to form the interconnect ball (74).

Electrical interconnect and method for forming the same

A method for improving the bonding characteristics of TAB semiconductor packages to circuit boards is achieved by plating additional amounts of tin on the TAB semiconductor package leads after final package assembly is complete. Residues from the plating step are removed from the package assembly to prevent contamination. Stresses that were developed in the plated material during the plating step are removed by heating the leads.

Method for plating tab leads in an assembled semiconductor package

A method fpr removing coatings from surfaces without damaging the underlying surface includes placing a surface having material to be removed thereon into a plasma reactor and exposing it to a gaseous plasma comprising a reactive halogen species. The reactive halogen species may be derived from one or more of many well known halogen gases. An optional step of cleaning the coating prior to exposure to the halogen plasma is recommended.

Plasma removal of unwanted material

A method for removing nitride coatings from metal tooling and mold surfaces without damaging the underlying base metal includes placing the nitride coated metal surface into a plasma reactor and subjecting it to a gaseous plasma comprising a reactive fluorine species. The reactive fluorine species may be derived from one or more of many well known gases. An optional step of cleaning the nitride coating is recommended.

Growing community of inventors

Mesa, AZ, United States of America

George F Carney