Mellanox Technologies Tlv Ltd.

Mellanox Technologies, Ltd.

Intel Corporation

George Elias

Barak Gafni

Itamar Rabenstein

Benny Koren

Liron Mula

Lion Levi

Niv Aibester

Eyal Srebro

Sagi Kuks

Ido Bukspan

Amiad Marelli

Noam Katz Abramovich

Gil Levy

Zachy Haramaty

Miriam Menes

Roy Kriss

Oded Zemer

Ofir Merdler

Aviv Kfir

Eitan Zahavi

Amir Roitshtein

Ran Ravid

Alon Webman

Freddy Gabbay

Oded Wertheim

Shachar Bar Tikva

Idan Matari

Ido Bukshpan

Yoav Benros

Eran Rubinstein

Elad Mentovich

Ronny Ronen

Ilan Pardo

Gil Bloch

Adi Yoaz

Ido Bourstein

Hillel Chapman

Yuval Shpigelman

Lavi Koch

Shahaf Shuler

Amit Kazimirsky

Maty Golovaty

Evyatar Romlet

Gal Shohet

Harold Rosenstock

Noam Michaelis

Noam Avital

Oded Belfer

Noam Katz

Lior Abramovsky

Nizan Atias

Adi Maymon

Ofir Klara Altshul

Matisyahu Meier Goldmeier

A device includes one or more ports, one or more bandwidth shapers, and processing logic. The one or more ports are to connect to a communication network. A given bandwidth shaper is to: (i) when disabled, output traffic at an available full data rate, and (ii) when enabled, output the traffic at a specified shaper data rate lower than the available full data rate. The processing logic is to receive or generate notifications, which are indicative of average power that is consumed by the network device while outputting traffic through the one or more bandwidth shapers via the one or more ports, and based on at least some of the notifications, toggle at least one of the one or more bandwidth shapers between being enabled and disabled, to retain the average power consumed below a specified power budget.

Power consumption control by toggling bandwidth shapers

An apparatus includes a crossbar circuit that routes one or more packets between one or more ingress domains and one or more egress domains. The crossbar circuit includes sub-crossbar domains. An ingress control circuit associated with the one or more ingress domains may distribute packet data of the one or more packets to the sub-crossbar domains. An egress control circuit of the apparatus receives data bits associated with the packet data from egresses associated with the plurality of sub-crossbar domains. The egress control circuit may reorder or refrain from reordering the data bits based on an attribute associated with the distribution of the packet data.

Statistical high bandwidth and packet rate crossbar with low cell count

An apparatus includes a processor, configured to designate a memory region in a memory, and to issue (i) memory-access commands for accessing the memory and (ii) a conditional-fence command associated with the designated memory region. Memory-Access Control Circuitry (MACC) is configured, in response to identifying the conditional-fence command, to allow execution of the memory-access commands that access addresses within the designated memory region, and to defer the execution of the memory-access commands that access addresses outside the designated memory region, until completion of all the memory-access commands that were issued before the conditional-fence command.

Processor with conditional-fence commands excluding designated memory regions

A network device includes multiple ports, multiple buffer slices, a controller, and buffer control circuitry. The multiple ports are configured to communicate packets over a network. The multiple buffer slices are linked respectively to the multiple ports. The controller is configured to allocate a group of two or more of the buffer slices to a selected port among the ports. The buffer control circuitry is configured to buffer the packets, communicated via the selected port, in the group of the buffer slices, using zero-copy buffering.

Zero-copy buffering of traffic of long-haul links

A network element includes multiple ports and forwarding circuitry. The ports are configured to serve as network interfaces for exchanging packets with a communication network. The forwarding circuitry is configured to receive a multicast packet that is to be forwarded via a plurality of the ports over a plurality of paths through the communication network to a plurality of destinations, to identify a path having a highest latency among the multiple paths over which the multicast packet is to be forwarded, to forward the multicast packet to one or more of the paths other than the identified path, using a normal scheduling process having a first forwarding latency, and to forward the multicast packet to at least the identified path, using an accelerated scheduling process having a second forwarding latency, smaller than the first forwarding latency.

Low-latency processing of multicast packets

One or more blocks of dynamic random access memory are embedded together with a processor and a data bus on an integrated circuit. The data bus has a bandwidth b for general operation including memory access, the block of dynamic random access memory further requiring data refresh at a refresh rate r. The block thus forms an eDRAM on the integrated circuit, typically an ASIC. A refresh controller embedded with the eDRAM may control refresh by clocking the data bus at a rate higher than the rate of the data bus to accommodate both the required memory access and the required data refresh.

EDRAM refresh apparatus and method

An Integrated Circuit (IC) includes multiple ports and packet processing circuitry. The ports are configured to serve as ingress ports and egress ports for receiving and transmitting packets from and to a communication network. The packet processing circuitry is configured to forward the packets between the ingress ports and the egress ports, to read an indication that specifies whether the IC is to operate in an internal buffer configuration or in an off-chip buffer configuration, when the indication specifies the internal buffer configuration, to buffer the packets internally to the IC, and, when the indication specifies the off-chip buffer configuration, to configure one or more of the ports for connecting to a memory system external to the IC, and for buffering at least some of the packets in the memory system, externally to the IC.

Reusing switch ports for external buffer network

A network element includes output ports, a crossbar fabric and a scheduler. The output ports are organized in groups of multiple output ports selectable over predefined time slots in accordance with a cyclic mapping assigned to each group. In each time slot, the crossbar fabric routes to fabric outputs data received from the buffers via fabric inputs, in accordance with a routing plan. The scheduler determines and applies the routing plan for transmitting packets from the buffers to the communication network via the crossbar fabric and output ports. When in a given time slot, a required readout rate from a given buffer exceeds a maximum rate, the scheduler selects a group of the output ports to which the given buffer is routed in that time slot, and modifies the cyclic mapping for that group to reduce the required readout rate from the given buffer in the given time slot.

Throughput in a crossbar network element by modifying mappings between time slots and ports

A method includes obtaining (i) an operating-temperature profile of a hardware processing sub-unit (HPSU) of a network element as a function of time, and (ii) a dependence of an Equivalent Reliability Time (ERT) of the HPSU on operating temperature. The operating-temperature profile is weighted using the dependence of the ERT on operating temperature, to estimate an effective ERT of the HPSU. An operating condition of the HPSU in the network element is modified, depending on the effective ERT.

Raising maximal silicon die temperature using reliability model

Communication apparatus includes multiple ports configured to serve as ingress and egress ports, such that the ingress ports receive packets from a packet data network for forwarding to respective egress ports. The ports include an egress port configured for connection to a network interface controller (NIC) serving multiple physical computing units, which have different, respective destination addresses and are connected to the NIC by different, respective communication channels. Control and queuing logic is configured to queue the packets that are received from the packet data network for forwarding to the multiple physical computing units in different, respective queues according to the destination addresses, and to arbitrate among the queues so as to convey the packets from the queues via the same egress port to the NIC, for distribution to the multiple physical computing units over the respective communication channels.

Switch with controlled queuing for multi-host endpoints

A method for packet generation includes designating a group of one or more ports, from among multiple ports of one or more network elements, to perform the packet generation. A circular packet path, which traverses one or more buffers of the ports in the group, is configured. A burst of one or more packets is provided to the group, so as to cause the burst of packets to repeatedly traverse the circular packet path. A packet stream, including the repeated burst of packets, is transmitted from one of the ports.

Network switch operating as packet generator

A method for communication includes receiving and forwarding packets in multiple flows to respective egress interfaces of a switching element for transmission to a network. For each of one or more of the egress interfaces, in each of a succession of arbitration cycles, a respective number of the packets in each of the plurality of the flows that are queued for transmission through the egress interface is assessed, and the flows for which the respective number is less than a selected threshold to a first group, while assigning the flows for which the respective number is equal to or greater than the selected threshold are assigned to a second group. The received packets that have been forwarded to the egress interface and belong to the flows in the first group are transmitted with a higher priority than the flows in the second group.

Adaptive flow prioritization

Communication apparatus includes multiple interfaces connected to a packet data network and at least one memory configured as a buffer to contain packets received through the ingress interfaces while awaiting transmission to the network via respective egress interfaces. Processing circuitry is configured to identify data flows to which the data packets that are received through the ingress interfaces belong, to assess respective bandwidth characteristics of the data flows, and to select one or more of the data flows as candidate flows for mirroring responsively to the respective bandwidth characteristics. The processing circuitry selects, responsively to one or more predefined mirroring criteria, one or more of the data packets in the candidate flows for analysis by a network manager, and sends the selected data packets to the network manager over the network via one of the egress interfaces.

Multi-stage selective mirroring

A switching device includes a plurality of ports and a switching core, which is coupled to transfer data packets between ingress and egress ports. Switching logic maintains a descriptor queue containing respective descriptors corresponding to the data packets that have been received and queued by the ports, and responsively to the respective descriptors, instructs the switching core to transfer the queued data packets between the ports. Port logic, which is associated with each port, is configured, upon receipt of a data packet from the network at the port, to signal the switching logic to place a descriptor corresponding to the data packet in the descriptor queue and, upon identifying the data packet as meeting a predefined criterion, to convey a request to the switching logic, bypassing the descriptor queue, to instruct the switching core to transfer the data packet immediately to an egress port.

Packet switch with reduced latency

Communication apparatus includes a plurality of interfaces for receiving and transmitting data packets from and to a network and a memory, which receives and stores context data with respect to multicast groups. Packet processing circuitry establishes reliable connections over the network with the receiving nodes in the multicast groups, and upon receiving from a packet source on the network an incoming unicast packet containing multicast data and containing multicast metadata that identifies a multicast group, sends an acknowledgment of the incoming unicast packet to the packet source, reads the context data from the memory with respect to the identified multicast group, and transmits multiple outgoing unicast packets containing the multicast data via respective egress interfaces to the receiving nodes in the multicast group over the reliable connections.

Switch-based reliable multicast service

Growing community of inventors

Tel Aviv, Israel

George Elias