Infineon Technologies Ag

George Efthivoulidis

Peter Thurner

Alexander Melzer

Bernd Zimek

Rainer Findenig

Francesco Lombardo

Thomas Santa

Tony Gschier

A radar monolithic microwave integrated circuit (MMIC) includes a trigger encoder configured to receive a clock signal comprising a plurality of clock pulses having a fixed amplitude and a trigger signal configured to indicate trigger events. The trigger encoder is configured to encode the trigger signal into the clock signal to generate a distributed clock signal by skipping at least one clock pulse of the plurality of clock pulses to indicate a trigger event. The radar MMIC is configured to output the distributed clock signal having the at least one clock pulse skipped to indicate the trigger event. The radar MMIC is configured to receive the distributed clock signal as a received distributed clock signal. The radar MMIC further includes a radar operation controller configured to detect the trigger event based on the received distributed clock signal and initiate a radar operation based on detecting the trigger event.

Trigger signaling through a clock signal in cascading radar systems

A radar system is provided that includes a radar monolithic microwave integrated circuit (MMIC). The radar MMIC includes a plurality of radar signal channels; and at least one sensor configured to measure a physical parameter related to a temperature of the radar MMIC, and to generate sensor data corresponding to measured values of the physical parameter; and a controller configured to receive the sensor data from the at least one sensor, and to determine a channel operation of the plurality of radar signal channels, including selectively disabling at least a first radar signal channel of the plurality of radar signal channels and selectively enabling at least a second radar signal channel of the plurality of radar signal channels based on the measured values.

Dynamic radar signal channel deactivation in a cascaded radar system for active temperature control

A phase-locked loop (PLL) includes a detector configured to generate an error signal based on a difference between a reference signal and an output signal, a charge pump configured to generate current pulses based on the error signal, a loop filter configured to generate a control voltage based on the current pulses, and a voltage-controlled oscillator (VCO) configured to generate the output signal at a frequency which is a function of the control voltage. The loop filter includes a capacitive voltage divider configured to reduce the control voltage from a range that falls within a voltage domain of the charge pump to a range that falls within a voltage domain of the VCO, the voltage domain of the charge pump being greater than the voltage domain of the VCO.

PLL filter having a capacitive voltage divider

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Graz, Austria

George Efthivoulidis