Micron Technology Incorporated

Round Rock Research, LLC

Micron Communications, Inc.

Keystone Technology Solutions, LLC

Lockheed Martin Corporation

George Edward Pax

David K Ovard

John R Tuttle

Robert R Rotzoll

James E O'Toole

Mark E Tuttle

Brian P Higgins

Kevin M Devereaux

Tyler A Lowrey

Shu-Sun Yu

Roy Edgar Greeff

Thomas H Kinsley

Chan H Yoo

Gregory A King

Randon K Richards

Yogesh Sharma

Jonathan Scott Parry

David Howard Allen

Charles K Snodgrass

Timothy Mowry Hollis

Dan M Griffin

Brent Keeth

Troy A Manning

Brian L Johnson

Eric J Stave

Ronnie M Harrison

Joo S Choi

Dragos Dimitriu

Greg King

Terry R Lee

Aaron Preston Boehm

Matthew Alan Prather

Tyler A Lowery

Cliff Wood, Jr

Hui Fu

Systems, apparatuses, and methods relating to memory devices and packaging are described. A device, such as a dual inline memory module (DIMM) or other electronic device package, may include a substrate with a layer of graphene configured to conduct thermal energy (e.g., heat) away from components mounted or affixed to the substrate. In some examples, a DIMM includes an uppermost or top layer of graphene that is exposed to the air and configured to allow connection of memory devices (e.g., DRAMs) to be soldered to the conducting pads of the substrate. The graphene may be in contact with parts of the memory device other than the electrical connections with the conducting pads and may thus be configured as a heat sink for the device. Other thin, conductive layers of may be used in addition to or as an alternative to graphene. Graphene may be complementary to other heat sink mechanisms.

Memory modules and memory packages including graphene layers for thermal management

Systems, apparatuses, and methods for thermal dissipation on or from an electronic device are described. An apparatus may have a printed circuit board (PCB) having an edge connector. At least one integrated circuit device may be disposed on a surface of the PCB. A tubular heat spreader may be disposed along an edge of the PCB opposite the edge connector.

Tubular heat spreaders for memory modules and memory modules incorporating the same

Systems, apparatuses, and methods for operating a memory device or devices are described. A memory device or module may introduce latency in commands to coordinate operations at the device or to improve timing or power consumption at the device. For example, a host may issue a command to a memory module, and a component or feature of the memory module may receive the command and modify the command or the timing of its execution in manner that is invisible or non-disruptive to the host while facilitating operations at the memory module. In some examples, components or features of a memory module may be disabled to effect or introduce latency in operation without affecting timing or operation of a host device. A memory module may operate in different modes that allow for different latencies; the use or introduction of latencies may not affect other features or operability of the memory module.

Methods for memory power management and memory devices and systems employing the same

Semiconductor packages with pass-through clock traces and associated devices, systems, and methods are disclosed herein. In one embodiment, a semiconductor device includes a package substrate including a first surface having a plurality of substrate contacts, a first semiconductor die having a lower surface attached to the first surface of the package substrate, and a second semiconductor die stacked on top of the first semiconductor die. The first semiconductor die includes an upper surface including a first conductive contact, and the second semiconductor die includes a second conductive contact. A first electrical connector electrically couples a first one of the plurality of substrate contacts to the first and second conductive contacts, and a second electrical connector electrically couples a second one of the plurality of substrate contacts to the first and second conductive contacts.

Semiconductor packages with pass-through clock traces and associated systems and methods

Apparatus and methods are provided for operating a non-volatile memory module. In an example, a method can include filling a first plurality of pages of a first non-volatile memory with first data from a first data lane that includes a first volatile memory device, and filling a second plurality of pages of the first non-volatile memory device with second data from a second data lane that includes a second volatile memory device. In certain examples, the first plurality of pages does not include data from the second data lane.

Non-volatile memory module architecture to support memory error correction

An apparatus is provided, comprising a plurality of memory devices and a buffering device that permits memory devices with a variety of physical dimensions and memory formats to be used in an industry-standard memory module format. The buffering device includes memory interface circuitry and at least one first-in first-out (FIFO) or multiplexer circuit. The apparatus further comprises a parallel bus connecting the buffering device to the plurality of memory devices. The parallel bus includes a plurality of independent control lines, each coupling the memory interface circuitry to a corresponding subset of a plurality of first subsets of the plurality of memory devices. The parallel bus further includes a plurality of independent data channels, each coupling the at least one FIFO circuit or multiplexer circuit to a corresponding subset of a plurality of second subsets of the plurality of memory devices.

Memory devices, modules and systems having memory devices with varying physical dimensions, memory formats, and operational capabilities

Systems, apparatuses, and methods for thermal dissipation on or from an electronic device are described. For example, a memory module may have a printed circuit board (PCB) having an edge connector, a plurality of memory devices disposed on a surface of the PCB, and a tubular heat spreader disposed along an edge of the PCB opposite the edge connector. The tubular heat spreader may comprise a tubular portion open at both ends thereof to permit the through flow of a cooling gas; and two planar elements extending in parallel away from the tubular portion and configured to provide a friction fit with the memory module. Each of the planar elements may be configured to convey thermal energy from the memory module to the tubular portion.

Techniques for a non-volatile memory module are provided. In an example, an apparatus can include a first memory device comprising a first type of memory media, a second memory device comprising a second type of memory media, and a controller. The controller can transfer data from the first memory device to the second memory device based at least in part on loss of system power to the apparatus while operating on power provided by a backup power source, restore the data from the second memory device to the first memory device based at least in part on the system power to the apparatus being re-established, identity chip failure of the second memory device, the chip failure based at least in part on restoring the data from the second memory device to the first memory device, and operate the apparatus based at least in part on the chip failure identified.

Memory devices having heat spreaders are disclosed herein. In one embodiment, a memory device includes first memories coupled to a front side of a substrate, second memories coupled to a back side of the substrate, and a flexible heat spreader. The flexible heat spreader can include graphite and is coupled to back side surfaces of the first and second memories to dissipate heat generated by the first and second memories.

Heat spreaders for use with semiconductor devices

One embodiment of the present disclosure describes a loopback network including a loopback datapath and a plurality of memory devices. The plurality of memory devices may include a first memory device coupled to a first trunk connector of the first loopback datapath via a first branch connector. The plurality of memory devices may also include a second memory device coupled to the first trunk connector of the first loopback datapath via a second branch connector. When data communicated with the first memory device is targeted by loopback parameters, the first memory device may output a first loopback data signal generated based at least in part on the first data to the first loopback datapath, and the second memory device may block output from the second memory device to the first loopback datapath.

Memory device loopback systems and methods

A computing system including multiple integrated circuit memory devices is described. One or more command and address buses are connected to the memory devices to transmit command and address signals to each memory device. Multiple clock lines are connected to the multiple memory devices in a tree structure to transmit multiple clock signals to these memory devices. The tree structure allows each distributed clock signal to be individually trained such that the multiple clock signals provide each memory device with a clock signal that is temporally aligned with the command and address signals as received by that memory device.

Clock tree structure in a memory system

Growing community of inventors

Boise, ID, United States of America

George Edward Pax