Xerox Corporation

George E Mager

Frank M Nelson

Robert E Markle

Lamar T Baker

Warren L Hall

George K Tu

John W Daughton

Edward L Steiner

James M Donohue

Stephen P Wilczek

Kenneth Gillett

Charles P Holt

Kenton W Fiske

Donald S Post

Philip Richardson

Thomas Criswell

Vernon E Rochat

Steven L Reid

A copy reproduction machine is subdivided into discrete operating modules and coupled together by a shared communication line over which operating messages from and to the modules are transmitted. Each module includes a receiver for intercepting and capturing messages bearing the module's address and a transmitter for transmitting messages from the module and addressed to other modules over the shared communication line.

Message transmitting system for reproduction machines and copiers

A mask programmable logic array (PLA) for producing a particular digital output given a certain digital input. The input signals to the PLA first pass through a series of AND gates resulting in a predetermined number of product terms being formed. The product signals then pass through a set of OR gates to become the final output signals. In the subject invention, the AND gates and OR gates are implemented through the use of NOR-NOR logic. A first set of NOR gates is implemented in an array to receive input signals and to produce product terms. A second and third set of NOR gates form two arrays. These two arrays are then located on either side of the first array to receive selected product signals in order to produce final output signals. In effect the OR portion of the PLA has been split into two arrays.

Split programmable logic array

A method and apparatus for bit manipulation in a digital processor being suitable for executing a plurality of instructions stored in a memory and carried from said memory in accordance with a plurality of machine cycles, each of said instructions including an operational code. A decoder generates a bit mask in response to an operational code. The bit mask generated is in binary digits which are the complement of 2.sup.i where i is the number in base 10 represented by the three least significant bits of the operational code. A register stores the particular bit-mask. An additional register stores a word in which a bit is to be manipulated. Logic circuitry performs one or more logic operations on the output of the registers whereby a desired bit in said word is manipulated. The output of the logic circuitry may be tested and depending on the result, a jump to a particular instruction stored in the memory may be made.

Bit manipulation circuitry in a microprocessor

The chip topography of an MOS microprocessor chip. The chip architecture includes an internal data bus and an internal address bus. Input/output circuitry is located along the top edge of the chip and is coupled to the data bus. Output circuitry is located along the bottom edge and coupled to the address bus. A program storage area which includes a ROM is located in the lower left hand corner of the chip. The ROM contains instruction words for defining the operation of the microprocessor. A data storage area which includes a RAM is located in the upper left hand corner of the chip and is coupled to the data bus. An ALU area is located to the right of the data storage area and is coupled to the data bus for performing arithmetic and logic operations on data. A condition decode ROM located in the approximate center of the chip is coupled to the data bus and is used for decoding a condition field of an instruction word received from the ROM. A bus control area is located in the upper right hand corner of the chip. A programmed control area is located between the ALU area and the bus control area in the upper right hand portion of the chip and is coupled to the data bus for receiving instruction words from the program storage area and for generating commands which define the operation of the microprocessor in response to the instruction words. A clock/T-counter is located in the lower right hand corner and is used for synchronizing data signal flow in the micrprocessor. A stack area is located in the lower right hand portion of the chip. Within this stack area are various registers located from top to bottom as follows; write X circuitry, an X register a stack array, stack read/write circuitry, a memory address register, and an incrementer. A stack control is located between the aforementioned stack circuitry and the right hand edge. In addition, a RAM decode is located between the RAM and the left hand edge, a ROM column decode is located between the ROM and the bottom edge, and a ROM row decode is located between the ROM and the stack area.

Chip topography for MOS integrated circuitry microprocessor chip

An auxiliary ROM memory system which is hierarchied for providing for the contingency of additional read-only memory control program storage requirements in excess or in lieu of the predetermined ROM memory provided on-board a microprocessor based central processing unit module, and a read-only memory altering capability utilizing programmable read-only memory to expedite the implementation/installation of changes to the ROM bit patterns. The alterable PROM storage comprises bulk PROM memory including a first PROM set that is mutually exclusive as to existing on-board ROM memory for addressably branching to code extensions and/or in-line code insertions, and/or a second PROM set that is mutually inclusive as to existent on-board and contingent ROM memory for decodably addressing large-scale code overlays thereto. In addition, the alterable PROM storage comprises patch PROM for addressing, through multi-leveled decoding, small-scale code overlays to the on-board and contingent ROM memory for single in-line bit pattern alterations. Conflicting memory requests involving addresses recognized by more than one of the supra memory categories, when enabled, are presented to a predetermined hierarchy of memory precedences for resolution thereof. Each of the enumerated memory categories of the auxiliary ROM memory system may be operative to have its population incremented or decremented without invalidating the above hierarchy of addressing.

Auxiliary ROM memory system

In a controller for a host machine such as an electrostatographic copier having a central processing unit module connected via a system bus to an input-output processing unit module, a direct memory access system functioning as part of the input-output processing unit module and operative to provide a high-speed means of refreshing and updating control registers in the host machine by direct accessing of memory in the central processing unit module. The direct memory access system may be programmed to synchronously refresh-update the host machine's control registers as in its normal mode and also asynchronously refresh-update the control registers as in the abnormal mode of a detected electrical disturbance in the electro-sensitive periphery surrounding the control registers, thus requiring restoring thereof. High-speed movement of data by the direct memory access system is achieved through dedicating a portion of random access memory in the central processing unit module for such accessing, and transferring control of the system bus from the central processing unit module to the direct memory access system. This enables data accessed through a fixed sequence of addresses from dedicated memory to be transferred directly to the host machine's control registers without incurring time constants that would otherwise be had if the data were to be manipulated by a central processor in the central processing unit module.

Direct memory access module for a controller

In a control module having a central processor coupled through a system bus including data, address and control lines to access a data memory, a direct access apparatus is included coupled through the system bus to request a hold of the central processor and upon acknowledgement for directly accessing the data memory through the system bus for directing the control registers of a host machine. Also included are a diriment element interfaced to the central processor for receipt of control signals on the system bus from the direct access apparatus for hold request and for transmission of first and second control signals on the system bus from the central processor for acknowledgement, and a timed protocol unit for supervising the data, address and control signals transported on the system bus. The timed protocol unit comprises an address control coupled through the system bus to the central processor for disenabling address signals upon receipt of the first acknowledgement signal on the system bus from the diriment element, and a data control coupled through the system bus to the central processor for bidirectionally disenabling data signals upon receipt of the second acknowledge signal on the system bus from the diriment element.

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Manhattan Beach, CA, United States of America

George E Mager