Motorola Corporation

George E Dykas

Kenneth W Hamilton

James A Lamb

Richard A Magerl

Johnny E Blankenship

William W Milleker

In a data transmission system, for communicating messages between a base station and a plurality of mobile stations, each mobile station includes a radio frequency transceiver and a programmable data terminal for sending and receiving predeterminedly formatted digitally encoded messages. A keyboard subsystem and character display subsystem are controlled by a programmable microprocessor subsystem which also processes received and transmitted messages. A transmit and receive system clock interrupts the operation of the microcomputer to process messages. The messages include a cyclical redundant check byte as well as a control number byte. Characters which are not editable blink. A terminal status display line is provided and a message received character is also provided. The system sets the system clock period to be the same for all data rates. Automatic restart of the system is provided as well as a means for detecting and generating a pseudo-random message preamble. Cursor positioning, memory interchange, and display keys are provided. Receipt and acknowledgement of various types of messages are also provided.

Programmable digital data terminal for mobile radio transceivers

An addressing circuitry for a dot matrix vertical scan plasma display includes a character row counter and a character column counter, a random access memory, a dot pattern generator, a parallel to series shift register, and a driver for the display. The addressing circuitry is responsive to a processor. Alpha-numeric digital characters to be displayed are read out of the memory in sequence in response to a sequence signal from the character row counter and the character column signal output. The words read out of the memory are converted into dot matrix pattern by the dot pattern generator and displayed on the plasma display via the parallel to serial shift register and driver. An offset adder is used when the number of character rows and the number of characters per row of the display are other than binary progression numbers in generating a sequence signal. The offset adder is interposed between the random access memory and the row and column outputs. The offset adder is of a design that eliminates the wasted character memory locations that would otherwise take place in its absence. The addressing circuitry includes control logic responsive to the processor unit and the random access memory for enabling the dot pattern generator to apply cursor, blinking or blanking control signals selectively to the display.

Addressing circuitry for a vertical scan dot matrix display apparatus

A two-way AM communications apparatus is provided with common circuitry for biasing the transmitter and receiver on and off alternately while minimizing the switching noise heard in the audio. The push-to-talk button enables either the transmitter or the receiver by means of a transmitter switching network which controls a receiver switching network. When the transmitter is enabled, the audio is muted through a fast-react, slow-decay circuit, and an OR gate and the power amplifier is enabled through a slow-react, fast-decay circuit and a NOR gate. Similarly, when the receiver is enabled, the power amplifier is disabled and the audio unmuted through the same circuitry. A first OR gate is coupled to the channel select switch and noise blanker or other radio circuit to trigger a one-shot multivibrator which in turn is coupled to second inputs of the NOR gate and first OR gates to provide brief audio mute (if receiving) or brief power amplifier disable (if transmitting) during switching periods.

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Vernon Hills, IL, United States of America

George E Dykas