Sanmina-sci Corporation

Sanmina Corporation

Hadco Santa Clara, Inc.

George Dudnikov, Jr

Nicholas Biunno

Franz Gisin

Atul Patel

Ken Ogle

Shinichi Iketani

Dale Kersten

Gregory J Schroeder

A multilayer printed circuit board is provided having a first dielectric layer and a first plating resist selectively positioned in the first dielectric layer. A second plating resist may be selectively positioned in the first dielectric layer or a second dielectric layer, the second plating resist separate from the first plating resist. A through hole extends through the first dielectric layer, the first plating resist, and the second plating resist. An interior surface of the through hole is plated with a conductive material except along a length between the first plating resist and the second plating resist. This forms a partitioned plated through hole having a first via segment electrically isolated from a second via segment.

Simultaneous and selective wide gap partitioning of via structures using plating resist

A novel method for manufacturing embedded a capacitive stack and a novel capacitive stack apparatus are provided having a capacitive core that serves as a structural substrate on which alternating thin conductive foils and nanopowder-loaded dielectric layers may be added and tested for reliability. This layering and testing allows early fault detection of the thin dielectric layers of the capacitive stack. The capacitive stack may be configured to supply multiple isolated capacitive elements that provide segregated, device-specific decoupling capacitance to one or more electrical components. The capacitive stack may serve as a core substrate on which a plurality of additional signaling layers of a multilayer circuit board may be coupled.

Embedded capacitive stack

Systems and methods for simultaneously partitioning a plurality of via structures into electrically isolated portions by using plating resist within a PCB stackup are disclosed. Such via structures are made by selectively depositing plating resist in one or more locations in a sub-composite structure. A plurality of sub-composite structures with plating resist deposited in varying locations are laminated to form a PCB stackup of a desired PCB design. Through-holes are drilled through the PCB stackup through conductive layers, dielectric layers and through the plating resist. Thus, the PCB panel has multiple through-holes that can then be plated simultaneously by placing the PCB panel into a seed bath, followed by immersion in an electroless copper bath. Such partitioned vias increase wiring density and limit stub formation in via structures. Such partitioned vias allow a plurality of electrical signals to traverse each electrically isolated portion without interference from each other.

Simultaneous and selective partitioning of via structures using plating resist

The protection of sensitive components on printed circuit boards by using planar transient protection material in one or more layers of a printed circuit board stackup is disclosed.

Substantially continuous layer of embedded transient protection for printed circuit boards

Protection for sensitive components on a printed circuit board by selectively depositing transient protection material on one or more layers of the printed circuit board is disclosed.

Selective deposition of embedded transient protection for printed circuit boards

Improved systems and methods for laser trimming resistors printed on a substrate layer are provided. An exemplary embodiment measures a resistance value for each annular resistor and sorts the annular resistors into one or more bins based on the measured resistance values and target resistance values associated with each resistor. A laser trim file may then be assigned to each bin based on a predictive trim formulation, where each laser trim file defines a set of configuration parameters for a laser drill to conform each resistor with their respective target value. The laser drill uses the laser trim files to trim the resistors within each bin in accordance with the laser trim file assigned to that bin.

Laser trimming of resistors

Improved systems and methods for laser trimming resistors are provided. An exemplary embodiment measures a resistance value for each resistor and sorts the resistors into one or more bins based on the measured resistance values and target resistance values associated with each resistor. A laser trim file may then be assigned to each bin based on a predictive trim formulation, where each laser trim file defines a set of configuration parameters for a laser drill to conform each resistor with their respective target value. The laser drill uses the laser trim files to trim the resistors within each bin in accordance with the laser trim file assigned to that bin.

Improved systems and methods for laser trimming annular resistors printed on a circuit board are provided. An exemplary embodiment measures a resistance value for each annular resistor and sorts the annular resistors into one or more bins based on the measured resistance values and target resistance values associated with each annular resistor. A laser trim file may then be assigned to each bin based on a predictive trim formulation, where each laser trim file defines a set of configuration parameters for a laser drill to conform each annular resistor with their respective target value. The laser drill uses laser trim files to trim the annular resistors within each bin in accordance with a laser trim file assigned to that bin.

Growing community of inventors

San Jose, CA, United States of America

George Dudnikov, Jr