Apple Inc.

George Cuan

Jerome Francis Duluk, Jr

Emerson S Fang

Richard E Hessel

Sushma Shrikant Trivedi

Vaughn Todd Arnold

Jack Benkual

Stephen L Dodgen

Hengwei Hsu

Jason Rupert Redgrave

Joseph P Bratt

Sidong Li

Matthew N Papakipos

Nathan D Tuck

Sam Ng

Zhaoyu Gong

Thomas Y Ho

Tuan Anh Nguyen

Abbas Rashid

Shun Wai Go

Abraham Mammen

Bo Hong

Joseph P Grass

Lindy Fung

Albert Suan-Wei Tsay

Thomas Y Yo

A deferred shading graphics pipeline processor and method are provided encompassing numerous substructures. Embodiments of the processor and method may include one or more of deferred shading, a tiled frame buffer, and multiple?stage hidden surface removal processing. In the deferred shading graphics pipeline, hidden surface removal is completed before pixel coloring is done. The pipeline processor comprises a command fetch and decode unit, a geometry unit, a mode extraction unit, a sort unit, a setup unit, a cull unit, a mode injection unit, a fragment unit, a texture unit, a Phong lighting unit, a pixel unit, and a backend unit.

Deferred shading graphics pipeline processor having advanced features

A deferred shading graphics pipeline processor and method are provided encompassing numerous substructures. Embodiments of the processor and method may include one or more of deferred shading, a tiled frame buffer, and multiple-stage hidden surface removal processing. In the deferred shading graphics pipeline, hidden surface removal is completed before pixel coloring is done. The pipeline processor comprises a command fetch and decode unit, a geometry unit, a mode extraction unit, a sort unit, a setup unit, a cull unit, a mode injection unit, a fragment unit, a texture unit, a Phong lighting unit, a pixel unit, and a backend unit.

Graphics processors and methods are described that encompass numerous substructures including specialized subsystems, subprocessors, devices, architectures, and corresponding procedures. Embodiments of the invention may include one or more of deferred shading, a bled frame buffer, and multiple-stage hidden surface removal processing, as well as other structures and/or procedures. Embodiments of the present invention are designed to provide high-performance 3D graphics with Phong shading, subpixel anti-aliasing, and texture- and bump-mappings.

Graphics processor with deferred shading

The present invention provides post tile sorting setup in a tiled graphics pipeline architecture. In particular, the present invention determines a set of clipping points that identify intersections of a primitive with a tile. The mid-pipeline setup unit is adapted to compute a minimum depth value for that part of the primitive intersecting the tile. The mid-pipeline setup unit can be adapted to process primitives with x-coordinates that are screen based and y-coordinates that are tile based. Additionally, to the mid-pipeline setup unit is adapted to represent both line segments and triangles as quadrilaterals, wherein not all of a quadrilateral's vertices are required to describe a triangle.

Apparatus and method for performing setup operations in a 3-D graphics pipeline using unified primitive descriptors

Three-dimensional computer graphics systems and methods and more particularly to structure and method for a three-dimensional graphics processor and having other enhanced graphics processing features. In one embodiment the graphics processor is a Deferred Shading Graphics Processor (DSGP) comprising an AGP interface, a command fetch & decode (,), a geometry unit (,), a mode extraction (,) and polygon memory (,), a sort unit (,) and sort memory (,), a setup unit (,), a cull unit (,), a mode injection (,), a fragment unit (,), a texture (,) and texture memory (,) a phong shading (,), a pixel unit (,), a backend unit (,) coupled to a frame buffer (,). Other embodiments need not include all of these functional units, and the structures and methods of these units are applicable to other computational processes and systems as well as deferred and non-deferred shading graphical processors.

Deferred shading graphics pipeline processor

Three-dimensional computer graphics systems and methods and more particularly to structure and method for a three-dimensional graphics processor and having other enhanced graphics processing features. In one embodiment the graphics processor is Deferred Shading Graphics Processor (DSGP) comprising an AGP interface, a command fetch decode (,), a geometry unit (,), a mode extraction (,) and polygon memory (,), a sort unit (,) and sort memory (,), a setup unit (,), a cull unit (,), a mode injection (,), a fragment unit (,), a texture (,) and texture memory (,) a phong shading (,), a pixel unit (,), a backend unit (,) coupled to a frame buffer (,). Other embodiments need not include all of these functional units, and the structures and methods of these units are applicable to other computational processes and systems as well as deferred and non-deferred shading graphical processors.

Growing community of inventors

Sunnyvale, CA, United States of America

George Cuan