Marvell International Limited

Other

George Chien

King Chun Tsai

Lawrence Tse

Xiaodong Jin

Alireza Shirvani-Mahdavi

Shuran Wei

Tyson Leistiko

Sang Won Son

Joseph Knapp

Leycheoh Lim

Qiong Sun

Yonghua Song

Yungping Hsu

Yuan-Ju Chao

Hsiao-Cheng Tang

Donghong Cui

Alireza Shirvani Mahdavi

A system including a component of a transceiver, a comparator, a counter, and a calibration circuit. The component receives an input signal comprising packets and based on the input signal, generates output signals to transmit the packets. The comparator compares the output signals to generate a comparison signal. The counter counts cycles of a clock signal to provide a count value. The control device, based on the comparison signal, transitions the counter between incrementing the count value and decrementing the count value. The calibration circuit operates in first and second calibration modes; during the first calibration mode, calibrates the component until the counter transitions a predetermined number of times between incrementing the count value and decrementing the count value; and during the second calibration mode, calibrates the component until (i) the counter transitions between incrementing and decrementing the count value, or (ii) counts a predetermined number of cycles.

Apparatus and method for calibrating a component of a transceiver via a calibration circuit operating in different calibration modes

A transceiver including a transceiver component with a first and second inputs and an output. The transceiver is configured to (i) receive an input signal having packets via the first input and (ii) generate output signals at the output based on the input signal. The transceiver further includes a first comparator configured to compare the output signals and generate a first comparison signal; a register configured to store the first comparison signal; a calibration circuit is configured to generate a current signal based on the first comparison signal to adjust a current in the transceiver component; and a signal generator is configured to generate a reference signal based on the current signal. The transceiver component is configured to (i) based on the current signal, adjust a performance parameter of the transceiver at times synchronized with the packets and (ii) generate the output signals based on the current signal and the reference signal.

Frame/packet-based calibration for wireless transceivers

A low noise amplifier includes an input stage. The input stage includes a first device configured to receive an input signal. A second device is connected to the first device. The second device has a predetermined input impedance. The input stage is configured so that a change in the input signal to the first device causes a linearly proportional change in a conductance of the first device. A voltage at a junction between the first device and the second device remains substantially constant due to the predetermined input impedance of the second device.

Method and apparatus for an LNA with high linearity and improved gain control

A receiver includes a Gilbert cell mixer comprising an input transconductance stage. The input transconductance stage includes first and second transistors receiving an input signal and providing a first gain characteristic that is substantially non-linear over an operating frequency range of the receiver. Third and fourth transistors receive the input signal and provide a second gain characteristic that is substantially non-linear over the operating range of the receiver. A combined gain characteristic of the input transconductance stage is based on the first and second gain characteristics and is substantially linear over the operating frequency range of the receiver.

Mixer gain calibration method and apparatus

Systems and methods are provided for calibrating the control mechanism in a communication circuit to allow the communication circuit to maintain a desired output power level. The communication circuit includes a variable gain adjustment circuit and a power amplifier, which operate together to provide an output power level. A control circuit controls the variable gain adjustment circuit based on a default gain parameter, a high power threshold, and a low power threshold. A calibration circuit in the control circuit calibrates a default gain parameter to provide a desired output power. A power detector can detect the desired output power level to provide an output power measurement. The calibration circuit calibrates upper and lower power thresholds to provide an acceptable range of power variation around the output power measurement.

Systems and methods for calibrating power regulated communication circuitry

Methods and apparatus are provided for performing loopback testing of integrated circuits ('ICs'). In an embodiment of the invention, an IC can be tested on an undiced wafer by coupling a wireless transmitter of the IC to a wireless receiver of the IC. Core circuitry of the IC can be controlled to cause the transmitter to send at least one signal to the receiver. Upon receipt of the at least one signal, the receiver can send a signal to the core circuitry, which can determine, and possibly record, whether the transmission and receipt were successful. The invention advantageously facilitates efficient testing of unpackaged ICs at the wafer level.

Methods and apparatus for integrated circuit loopback testing

A packet-based wireless transceiver that transmits and receives data packets comprises a receiver including a mixer that converts signal frequencies and a baseband circuit that communicates with the mixer and that includes an amplifier. A receiver voltage offset calibration circuit adjusts a receiver voltage offset at the baseband circuit at times synchronized with the data packets and includes a calibration signal generator that outputs calibration signals to first and second inputs of the baseband circuit and a calibration adjustment circuit that communicates with the calibration signal generator and that adjusts the calibration signal to reduce the voltage offset based on an output of the amplifier.

Circuits and methods are provided for generating reference currents. In one implementation, a circuit is provided that includes a first source and a current control circuit in communication with the first source. The first source generates a first reference current that is a ratio of a first reference voltage and an external resistance. The current control circuit produces a second reference current that is a ratio of a second reference voltage and the external resistance. The current control circuit produces the second reference current without being directly coupled to the external resistance.

Dual reference current generation using a single external reference resistor

A faceplate for a housing of a computing device including a processor includes a bezel with interior and exterior surfaces. The bezel removeably covers at least a portion of an opening defined by the housing. A wireless local area network (LAN) unit is mechanically coupled to the interior surface of the bezel and comprises a data interface that enables data transfer between the wireless LAN unit and the processor.

Faceplate including wireless LAN communications

A low noise amplifier (LNA) circuit includes a linear input stage including a first circuit that generates an output current and has a low input impedance. A device receives an input signal, communicates with the low impedance input of the first circuit, and includes a variable resistor having a resistance that varies based on the input signal.

A geometric ladder circuit produces a transfer function having substantially uniform steps measured in dB. Where the ladder has a plurality of substantially identical resistor rungs of a first resistance, one stile that is a conductor connecting the rungs, and another having a series of substantially identical resistors of a second resistance, then for identical currents injected at different rungs, the output signal at an end of the ladder is attenuated by a number of substantially equal steps, one for each rung between input and output. For a ladder with a base rung R, an output at an end opposite the base rung, stile resistors of resistance &#x3b1;R, and other rungs all of resistance (1+(1/&#x3b1;))R, the step size is 20 log(1+&#x3b1;).

Geometric ladder circuit with linear-in-dB transfer function

An analog signal processing circuit comprises a bias circuit, a first circuit including a control input that communicates with the bias circuit, a first terminal that generates an output current, and a second terminal, and a device that communicates with the second terminal of the first circuit, that includes a variable resistor, and that has a resistance that is modulated in response to an input signal to the analog signal processing circuit.

A gain calibration circuit comprises a generator that generates a constant overdrive voltage that biases a radio frequency (RF) mixer. A reference signal generator generates a reference signal. A comparator receives the reference signal and a second signal that is a function of a mixer bias current flowing through the RF mixer and that generates a difference signal. An adjustment circuit adjusts a transconductance gain of the RF mixer based on the difference signal.

An external bay faceplate for a computer case which includes an integrated wireless LAN unit is disclosed. In particular, a faceplate is provided which includes a bezel defining interior and exterior major surfaces arranged to removably cover at least a portion of an external bay opening in a computer case, and a wireless LAN unit mechanically coupled to a surface of said bezel and including a data interface enabling data transfer between the wireless LAN unit and the information processor within the computer case. Several protocols and wired interfacing techniques, including various flavors of USB, FireWire, ethernet, and disk or removable media drive transmission may be used in conveying data between the information processor and the wireless LAN unit. The wireless LAN unit may be conveniently integrated with a blank faceplate covering substantially all of the external bay opening, or a drive faceplate, such as a removable media faceplate.

Growing community of inventors

Cupertino, CA, United States of America

George Chien