General Electric Company

Martin Marietta Corporation

George C Pifer

Mike F Chang

Bantval J Baliga

Peter V Gray

Simon A Zaidel

William F Kopp

Terrence S Alcorn

The invention relates to an air bridge and an evaporative process for making air bridges. A first layer of photoresist is patterned to create two openings over the contacts to be connected, separated by a strip of photoresist. The photoresist strip is hard baked to allow it to soften and to cause further cross linking. The softening allows surface tension to reshape the photoresist strip to create a gradually sloping arcuate surface between contact openings upon which a metal layer of nearly constant thickness may be evaporated. A second layer of photoresist is then applied, and patterned to create a single large opening embracing both contacts and the now arcuate hard baked photoresist strip. An arch within the large opening connecting both contacts is formed by evaporation. Excess metal and both photoresist layers are then removed, leaving a novel, arch shaped air bridge.

Process for making air bridges for integrated circuits

A self aligned method of fabricating a self aligned semiconductor device employs an initial step in which a first window having an inner perimeter and outer perimeter is opened through a first protective layer situated atop a semiconductor substrate, to divide the substrate into three separate zones. The window exposes a first surface portion of the semiconductor substrate and circumferentially defines or encompasses a second central portion of the protective layer as well as a second unexposed surface portion of the substrate. A third surface portion of the substrate lies beyond the outer perimeter of the first window. Precisely aligned substrate regions of the same or different conductivity type can be established by using differentially etchable materials to mask designated surface portions of the substrate.

Method of fabricating self aligned semiconductor devices

A semiconductor device, such as a MOSFET or IGT, with a deep base region having a high dopant concentration at least as high as 5.times.10.sup.19 atoms per cubic centimeter and a method of fabrication are disclosed. The novel method involves formation of the deep base region at a later stage in the fabrication and reduces the leaching of dopant from the deep base region, as well as achieving greater control over the dopant concentration in the deep base region. Further, the increased dopant concentration in the deep base region lowers the base shunt resistance of the device to provide improved electrical ruggedness. For IGTs, parasitic thyristor action is reduced.

Semiconductor device and method of fabrication

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North Syracuse, NY, United States of America

George C Pifer