International Business Machines Corporation

George Antony

Sridhar H Rangarajan

Sourav Saha

Vinay K Singh

Christopher J Berry

Ricardo H Nigaglioni

Mary Prilotski Kusko

Haoxing Ren

Alexander Joel Suess

Thomas Edward Rosser

Rahul Rao

Pinaki Chakrabarti

Naiju K Abdul

Ankit N Kagliwal

Shrinivas Shenoy

A method, a computer system, and a computer program product for scan chain wirelength optimization is provided. Embodiments of the present invention may include obtaining root nodes details from the root nodes. Embodiments of the present invention may include optimizing a connectivity of the root nodes. Embodiments of the present invention may include identifying a best start node and a best end node for each of the root nodes. Embodiments of the present invention may include optimizing child nodes in each of the root nodes. Embodiments of the present invention may include determining that a wirelength of a full tour is shorter or longer than a nearest neighbor. Embodiments of the present invention may include applying or skipping a solution.

Scan chain wirelength optimization using Q-learning based reinforcement learning

A computer-implemented method for modifying an original design of an integrated circuit in accordance with an engineering change order (ECO) design includes cloning complex logic gate having multiple logic functions with cloned logic gates in parallel with the corresponding complex logic gates in the original design and the ECO design and expanding each cloned logic gate to corresponding base functionality logic gates to provide an expanded original design and an expanded ECO design using the processor. The method also includes modifying at least a portion of the expanded original design to have a circuit topology that is the same as the expanded ECO design in order to have an input from the expanded original design to an output structure be the same as the input from the expanded ECO design to the output structure in response to an expanded original design input and an expanded ECO design input being non-equivalent.

Integrated circuit logic extraction using cloning and expansion for engineering change order

A method, executed by a computer, includes receiving a scan chain design comprising a plurality of parallel scan chains, each parallel scan chain comprising one or more serially connected single-bit registers, each parallel scan chain having a scan chain length. The plurality of parallel scan chains are interspersed with a plurality of stumpmuxes that enable access to the plurality of parallel scan chains and segment each parallel scan chain into a plurality of scan chain segments. The method further includes conducting a determining operation comprising determining a parallel scan chain having a longest scan chain length, and conducting a swapping operation comprising swapping scan chain segments attached to a selected stumpmux to reduce the longest scan chain length and produce an updated scan chain design. A computer system and computer product corresponding to the above method are also disclosed herein.

Scan chain latency reduction

A method and system to identify a region of a design block of an integrated circuit for redesign are described. The method includes dividing the design block into grids, each of the grids including a corresponding number of logic elements. The method also includes filtering each of the grids based on a specified criteria, the filtering including determining a number (B) of the corresponding logic elements among a total number (A) of the logic elements in each grid that meet the specified criteria. The region is a set of two or more of the grids based on a result of the filtering.

Critical region identification

A computer implemented method for designing an integrated circuit includes receiving a netlist. The method also includes receiving physical layout information related to an integrated circuit based on the on the netlist and receiving an engineering change order (ECO) that changes at least one logical component of the physical layout. The method further includes forming two or more possible solutions to achieve the ECO, ranking the two or more possible solutions based on two or more factors and selecting the highest ranked solution.

Placement aware functional engineering change order extraction

Aspects of the invention provide for spare latch distribution for an integrated circuit design. In one embodiment, aspects of the invention include a method of generating a computer system for spare latch distribution in an integration circuit design, the method including: providing a computer system operable to: receive design data for the integrated circuit design, the design data including a plurality of latches; segment the integrated circuit design into a plurality of equal sections; determine a latch density within each of the equal sections; and determine a number of spare latches, based on the latch density, for each of the equal sections. Further, it is understood that the above are performed for each clock domain within the integrated circuit design.

Spare latch distribution

A computer-implemented method of determining threshold voltage levels within a macro of integrated circuit cells. In one embodiment, the method includes: referencing a library of the integrated circuit cells in the macro; estimating a leakage power and a dynamic power for a first integrated circuit cell in the macro; comparing the leakage power with the dynamic power; switching the first integrated circuit cell to a low threshold voltage level in response to determining the dynamic power is greater than the leakage power; and updating the library with a voltage level of the first integrated circuit cell.

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Kerala, India

George Antony