Qorvo Us, Inc.

Equal1.labs Inc.

Rf Micro Devices (cayman Islands), Ltd.

Rf Micro Devices, Inc.

Qorvo International Pte. Ltd.

Amalfi Semiconductor Corporation

Triquint International Pte, Ltd.

Equal!.labs Inc.

Qirvo Us, Inc.

George Adrian Maxim

Baker P Scott

Dirk Robert Walter Leipold

Michael Albert Asker

Marcus Granger-Jones

Julio C Costa

Stephen James Franck

Nadim Khlat

Chong Woo

Hideya Oshima

Daniel Charles Kerr

Danny W Chang

Padmmasini Desikan

Merrill Albert Hatcher, Jr

Michael F Zybura

Kelvin Kai Tuan Yan

Jinsung Choi

John August Orlowski

Toshiaki Moriuchi

Robert Aigner

Gernot G Fattinger

Eric K Bolton

David E Reed

Jon Chadwick

Stephen Mobley

Mihai Murgulescu

Chu Hsiung Ho

Jungmin Park

Alexander Wayne Hietala

Kevin Wesley Kobayashi

Ruediger Bauder

Michael Carroll

Ying Shi

Christian Rye Iversen

Jayanti Jaganatha Rao

Ali Tombak

Hui Liu

Daniel Ho

Alireza Shirvani

Malcolm Smith

Ralph Christopher Nieri

Christopher T Brown

Ming Tsai

Wolfram C Stiebler

Tom Biedka

Dongmei Cao

Stephen Frank

Dirk Robert Walker Leipold

Desikan Padmmasini

A power amplifier system is disclosed having an N number of transistors coupled together drain-to-source between a supply node and a fixed voltage node, wherein a first one of the N number of transistors coupled nearest to the fixed voltage node is configured to operate as an amplifying device in an ON-mode, and remaining ones of the N number of transistors are configured to operate as cascode devices in the ON-mode and to operate as turned-off switches in an OFF-mode. A controller is configured to place the N number of transistors in the first mode when a radio frequency (RF) signal is to be amplified by the first one of the N number of transistors and to place the N number of transistors in the second mode when the RF signal is not to be amplified by the first one of the N number of transistors.

Power amplifier system

The present disclosure relates to a multi-level three-dimensional (3D) package with multiple package levels vertically stacked. Each package level includes a redistribution structure and a die section over the redistribution structure. Each die section includes a thinned die that includes substantially no silicon substrate and has a thickness between several micrometers and several tens of micrometers, a mold compound, and an intermediary mold compound. Herein, the thinned die and the mold compound are deposed over the redistribution structure, the mold compound surrounds the thinned die and extends vertically beyond a top surface of the thinned die to define an opening over the thinned die and within the mold compound, the intermediary mold compound resides over the thinned die and fills the opening within the inner mold compound, such that a top surface of the intermediary mold compound and a top surface of the mold compound are coplanar.

Multi-level 3D stacked package and methods of forming the same

Disclosed is a power amplifier system having a main amplifier with an input coupled to a main radio frequency (RF) input and an output connected to a main RF output, wherein the main amplifier exhibits a nonlinear gain characteristic with compression. At least one compression compensating amplifier has a signal input coupled to the common RF input and a signal output coupled to the common RF output.

Disclosed is a low noise amplifier system. Included is a main amplifier having a main input coupled to a RF input and a main output connected to an RF output and an impedance amplifier having an impedance input coupled to the RF input and an impedance output coupled to the RF output, wherein the impedance amplifier is configured to provide input impedance matching to the main amplifier. The impedance amplifier also provides a first noise path that passes through the impedance amplifier such that the noise generated by the impedance amplifier is substantially out of phase with the noise that passes through a second noise path that passes through the main amplifier.

Compact low noise amplifier system

The present disclosure relates to an amplifier system having an output amplifier stage with a signal input and output, and a varactor with a capacitive output that is coupled to the signal input for adjusting input capacitance. The amplifier system also includes push varactor bias circuitry with a bias level output that is coupled to a tuning input, and a bias control input. The push varactor bias circuitry is configured to adjust bias voltage at the tuning input and thereby adjust the capacitance at the signal input by way of the varactor and reduce signal distortion at the signal output in response to a distortion compensation signal received at the bias control input.

Amplifier system

A power amplifier using multi-path common-mode feedback loops for radio frequency linearization is disclosed. In one aspect, a complementary metal oxide semiconductor (CMOS) power amplifier containing cascoded n-type field effect transistors (NFETs) and cascoded p-type FETs (PFETs) may have a common-mode feedback network and provides bias voltages that are dynamically varying with the signal power to keep the output common-mode fixed around a half-supply level, while the small-signal and large-signal transconductances of the FET's are kept balanced. A further feedback network may be associated with the supply voltage to assist in providing a symmetrical supply signal. The symmetrical supply signal allows for supply variations without introducing distortion for the power amplifier stage.

Power amplifier using multi-path common-mode feedback loop

Disclosed is a low noise amplifier system. Included is a main amplifier having a main input coupled to a RF input and a main output connected to an RF output and an impedance amplifier having an impedance input coupled to the RF input and an impedance output coupled to the RF output, wherein the impedance amplifier is configured to provide input impedance matching to the main amplifier. The impedance amplifier also provides a first noise path that passes through the impedance amplifier such that the noise generated by the impedance amplifier is substantially out of phase with the noise that passes through a second noise path that passes through the main amplifier. A neutralization amplifier is configured to reduce parasitic capacitive loading within the first noise path.

Low noise amplifier with parasitic capacitance neutralization

A power amplifier system having a power amplifier stage with dynamic bias circuitry is disclosed. Also included is bias control circuitry having a compression sensor having a sensor input coupled to a RF signal output and a sensor output, wherein the compression sensor is configured to generate a gain deviation signal in response to a sensed deviation from a flat gain profile of the power amplifier stage. Further included is a bias driver that is configured to drive dynamic bias circuitry to adjust bias to the power amplifier stage to maintain the flat gain profile in response to the gain deviation signal.

A power amplifier includes an over-current protection loop and/or an over-voltage protection loop to assist in preventing operation outside a safe operation zone. In a further exemplary aspect, triggering of the over-current protection loop adjusts a threshold voltage for the over-voltage protection loop. In further exemplary aspects, the over-current protection loop may adjust not only a bias regulator, but also provide an auxiliary control signal that further limits signals reaching the power amplifier. In still further exemplary aspects, the over-voltage protection loop may operate independently of the over-current protection current loop or the over-voltage protection loop contribute to an over-current protection signal.

Power amplifier with protection loop

A power amplifier system is disclosed having a first amplifier with a high-power input and a high-power output. A second amplifier has a low-power input and a low-power output. A reconfigurable mode switch network has a first series switch branch coupled between the high-power output and an RF output, a first shunt branch is coupled between the RF output and a fixed voltage node, and a second series switch branch is coupled between the low-power output and a shared node of the first shunt branch. The shared node separates the first shunt branch into a first shared section that is between the RF output and the shared node and a second shared section that is between the shared node and the fixed voltage node.

Embodiments of an apparatus that includes a substrate and an inductor residing in the substrate are disclosed. In one embodiment, the inductor is formed as a conductive path that extends from a first terminal to a second terminal. The conductive path has a shape corresponding to a two-dimensional (2D) lobe laid over a three-dimensional (3D) volume. Since the shape of the conductive path corresponds to the 2D lobe laid over a 3D volume, the magnetic field generated by the inductor has magnetic field lines that are predominately destructive outside the inductor and magnetic field lines that are predominately constructive inside the inductor. In this manner, the inductor can maintain a high quality (Q) factor while being placed close to other components.

Advanced 3D inductor structures with confined magnetic field

Power amplifiers having improved gate oxide integrity are disclosed. In particular, a dynamic asymmetric cascode bias circuit is used to provide a bias signal to a cascode power amplifier stage. The bias signal swings in synchronicity with an output signal from the power amplifier stage. By having this dynamic bias signal, the gate-drain stress on the device is reduced, preserving gate oxide integrity. Preserving gate oxide integrity helps preserve the operational profile and extend device life, providing an enhanced user experience.

Power amplifier having improved gate oxide integrity

A protection circuit for an acoustic filter and/or a power amplifier is disclosed. In one aspect, the protection circuit includes a bidirectional coupler that helps secure a measurement of power at an antenna. The power measurement is compared to a threshold by a detector, and if the power measurement is above the threshold, a signal is sent that causes debiasing of a power amplifier stage, which reduces power levels of signals being amplified by the power amplifier stage and correspondingly lowers the power level going through a filter associated with the power amplifier stage. By lowering the power level going through the power amplifier stage and the filter, both elements are protected against over power conditions allowing functionality to be maintained.

Protection circuit for acoustic filter and power amplifier stage

A driving amplifier with low output impedance is disclosed. In one aspect, a driving amplifier stage that does not need an inter-stage impedance matching network between the driving amplifier stage and an output amplifier stage in a transmission chain may be achieved by providing stacking transconductance devices within the driving amplifier stage and reusing a supply current to provide an intermediate signal with high current but moderated voltage swing to drive the output amplifier stage. In specifically contemplated aspects, the stacked transconductance devices may be complementary metal oxide semiconductor (CMOS) field effect transistors (FETs).

Driving amplifier stage with low output impedance

Power amplifier with protection loops

Growing community of inventors

Saratoga, CA, United States of America

George Adrian Maxim