Nxp Usa, Inc.

George Adrian Ciusleanu

Michael Rohleder

David Allen Brown

Marcus Mueller

Richard Soja

Jeffrey Freeman

Frank Steinert

Andrey Kovalev

Marcel Achim

An embedded information system includes a load control circuit coupleable to an external memory that contains instructions and constant data (organized by variable sized load units, LUs, and where at least one property of a LU is specified within metadata) associated with application code of a software application, at least one processor configured to execute the at least one application code; an internal memory configured as main system memory in a first part and as a cache for storing the instructions and constant data for an execution of the at least one application code from the external memory in a second part. The load control circuit is configured to load the LUs associated with the at least one application code from the external memory with a granularity of a single LU into the internal memory. A cache control circuit, manages the second part, based on metadata corresponding to the LUs, by being configured to: observe the execution of the application code by detecting at least one of: an LU being executed, a change from one LU to another LU within the internal memory; load metadata information corresponding to a LU instance from the external memory or the internal memory, specify a next LU to be loaded by the load control circuit into the second part; and specify a next LU to be evicted from the second part when there is insufficient space for loading the next LU.

Embedded information system and method for memory management

A processor scheduling structure, a method and an integrated circuit are provided. In accordance with at least one embodiment, the processor scheduling structure comprises a processor circuit and an operating system task aware caching (OTC) controller circuit coupled to the processor circuit. The OTC controller circuit comprises a load request timer, a load sequence queue (LSQ), and a request arbiter. The timer and the LSQ are coupled to and provide inputs to the request arbiter. The processor circuit comprises an internal memory and a processor core. The OTC controller circuit is configured to schedule processor tasks for the processor circuit in accordance with both priority-based scheduling, using the LSQ, and time-triggered scheduling, using the load request timer.

Hardware for supporting OS driven observation and anticipation based on more granular, variable sized observation units

An integrated circuit is disclosed that includes a central processing unit (CPU), a random access memory (RAM) configured for storing data and CPU executable instructions, a first peripheral circuit for accessing memory that is external to the integrated circuit, a second peripheral circuit, and a communication bus coupled to the CPU, the RAM, the first peripheral circuit and the second peripheral circuit. The second peripheral circuit includes a first preload register configured to receive and store a first preload value, a first register configured to store first information that directly or indirectly identifies a first location where first instructions of a first task can be found in memory that is external to the integrated circuit, and a counter circuit that includes a counter value. The counter circuit can increment or decrement the counter value with time when the counter circuit is started. A first compare circuit is also included and can compare the counter value to the first preload value. The first compare circuit is configured to assert a first match signal in response to detecting a match between the counter value and the first preload value. The second peripheral circuit is configured to send a first preload request to the first peripheral circuit in response to an assertion of the first match signal. The first preload request identifies the location where the first instructions of the first task can be found in the external memory.

Hardware for supporting time triggered load anticipation in the context of a real time OS

A system, method, apparatus and integrated circuit are provided for collecting runtime performance data with a set of hardware timers under control of a dedicated hardware control register by connecting a central processing unit (CPU) and memory to a timer block bank having a plurality of timer instances which are selectively enabled and activated to collect runtime performance data during execution of application code by measuring specified software execution events, where the dedicated hardware control register includes a plurality of register fields for independently controlling activation behavior of the plurality of timer instances in response to a single write operation to all register fields in the hardware control register.

Hardware support for OS-centric performance monitoring with data collection

In a data processing system having a processor and a memory protection unit (MPU), a method includes scheduling, in the processor, a new process to be executed; writing a process identifier (PID) corresponding to the new process into storage circuitry of the MPU; in response to updating the storage circuitry with the PID, configuring the MPU with region descriptors corresponding to the new process; configuring, by an operating system of the processor, the processor to execute the new process in parallel with the configuring the MPU with the region descriptors; and when the configuring the MPU is complete, giving control to the new process to execute on the processor.

Growing community of inventors

Marasesti, Romania

George Adrian Ciusleanu