Rockwell International Corporation

Admiral Corporation

George A Watson

Keith M Bindloss

Kenneth E Garey

John Earle

Ricke Waylan Clark

James L Fuhrman

Dale E Folwell

Glen R Griffith

James E Rau

Rogell Van Wyk

Donald D Harenberg

Lawrence F Blank

Zane A Sandusky

David J Mueller

Daniel G Prysby

John V Moravec

Frank Avella

Ramon S Co

Stephen G Sawyer

A space vector data path for integrating SIMD scheme into a general-purpose programmable processor. The programmable processor uses a mode field in each instruction to specify, for each instruction, whether an operand is processed in either one of vector or scalar modes. The programmable processor also has a plurality of sub-processing units for receiving the operand and, responsive to an instruction as specified by the mode field in each instruction, for processing the operand in either one of the vector or scalar modes, wherein the vector mode indicates to the plurality of sub-processing units that there are a plurality of elements within the operand and the scalar mode indicates to the plurality of sub-processing units that there is but one element within the operand. For the vector mode, each element is processed by one of the sub-processing units concurrently to generate a vector result. For the scalar mode, the sub-elements of the one element operand are processed by the sub-processing units concurrently but independently to generate a scalar result.

Space vector data path

A register file connected to a data memory and an arithmetic logic unit for temporary storage of operands, and a method of managing such register file permits the register file to be used to maximum efficiency, and permits rapid task and context switching. Each register of the register file has an absolute address. A relative register address is read from the address field of the instruction being executed by the ALU, and an arithmetic calculation is performed on that relative register address and a register base address to obtain an absolute register address of the register to be accessed. Different sets of registers may be designated for different tasks or contexts. Each set of registers has its own base address. Once the task or context to which the instruction applies is determined, a calculation using the relative address from the instruction address field, and the corresponding register set base address may be performed to obtain the absolute address of the register to be accessed. Registers assigned to a different task or context may be virtually immediately accessed, or a set of registers for a particular task or context may be moved within the register file without affecting the instructions being executed by the ALU, by simply changing the base address used in the address computation.

Register file with multi-tasking support

The STREAMER FOR RISC DIGITAL SIGNAL PROCESSOR shown herein allows a CPU 46 to interface with a memory 60 via data registers 50. Pre-fetch and post-store of the correct address is determined by an address generator 58 according to a rule determined by a context register 52. An index indicative of this address is stored in an index register 54. The data, context, and index registers together form a streamer 56, streaming data between the CPU 46 and data memory 60. The rule of the context register 52 also drives a converter 62 for converting data between memory format and register format. The speed and flexibility of a RISC device is combined with the intensive memory access of a digital signal processor.

Triple register RISC digital signal processor

A debug port in accordance with the invention provides circuitry for enabling system (hardware and software) development within an inaccessible computer processor. In one embodiment, a debug port is incorporated within the internal logic of a single-chip, reduced instruction set signal processor referred to as the signal processor. A fully implemented debug port is comprised of five interacting functional elements: debug bus unit (DBU), debug command unit (DCU), debug instruction Unit (DIU), debug inject/extract unit (DJU), and a debug flow unit (DFU). The DBU provides circuitry for buffering data received from the signal processor and other functional elements within the debug port as well as accepting data from an external source. The DBU provides for off-chip connections. The DCU provides circuitry for decoding and executing debug commands received by the debug port. The DIU provides circuitry to insert one or more instructions with, or without, data into the instruction stream of the signal processor. The DJU provides circuitry for injecting external sources of information (e.g., an analog input signal, external control signals, or repetitious data signals) into the signal processor under program control. The DFU provides circuitry for monitoring program/task execution.

On-chip debug port

A frequency multiplexed system for coupling a plurality of individual telephone sets to at least one subscriber telephone line. The system includes a line adapter unit for controlling use of subscriber lines and for assigning the use of frequency bands to the individual telephone sets. The system includes a two-conductor interconnection cable for coupling to each of the telephone sets and to the line adapter unit. The system has a power-down mode in which the loss of external power allows each of the individual telephone sets to use the subscriber line. The line adapter unit and each of the individual telephone sets employ transconductance amplifiers so that modulated current signals are produced on the interconnection cable, thus allowing a plurality of voice signals to be summed together by voltage addition for conferencing between the telephone sets and the subscriber lines. One embodiment of the invention includes the production of a pilot reference signal on the interconnection cable by the adapter unit so that synchronous modulation and demodulation by each of the telephone sets is made possible.

Frequency multiplexed telephone system

There is disclosed a computer system including a storage means such as a random access memory (RAM) for receiving data to be displayed upon a display means, e.g. a color cathode ray tube, a microprocessor for control of the computer system operations, and viewer input devices such as a control stick or keyboard, whereby the viewer may respond selectively to the data displayed upon the display means. A limited capacity storage unit, illustratively in the form of a tape cassette, stores data in the form of a program for permitting the viewer to store useful material in the form of a repository, such as a Christmas list; the program to be displayed by the display means can assume any of a limitless number of programs and may be adapted to an exceptionally wide range of uses for the home, office or school. The computer system permits the viewer to respond as through the input devices, to the material being displayed, whereby subsequent material may be effected. To effect a variety of operations, the computer system includes a record/read device for receiving the storage unit, whereby the stored data thereon may be read out and stored in the RAM for subsequent use by the computer system. In this regard, graphic material to be displayed upon the display means is stored in select locations in the RAM to be selectively read out, dependent upon the image to be displayed. Further, there is included a second storage means in the form of a read-only memory (ROM) for storing utility sub-routines, whereby various operations of the computer system may be controlled.

Reactive computer system adaptive to a plurality of program inputs

An apparatus and method for predicting the time occurrence of the desired angular position of a rotating body, such as the crankshaft of an internal combustion engine. The apparatus includes means for storing a nonlinearly changing count that is set to a known starting value when the rotating body is at a known angular position. A computing means is included for computing the value of the count that corresponds to the time when the rotating body will be at the desired angular position. The computation is achieved by extrapolating from known count information based upon prior periods of angular displacement of the rotating body during periods of known duration. In addition, the apparatus includes means for reducing the error associated with extrapolating the desired angular position of a rotating body undergoing either acceleration or deceleration by basing the extrapolation on a known period of angular displacement that occurred earlier than the most recent period of rotation immediately prior to the extrapolation process.

Apparatus and method for extrapolating the angular position of a

An anti-skid control system for decreasing braking distance performance of a braked wheeled vehicle while maintaining the lateral stability thereof. The system is comprised of a digital data logic processor responsive to only wheel deceleration and wheel velocity of the braked vehicle for iteratively or alternatively preselectively attenuating and restoring an applied brake fluid pressure, so as to cause the brake system performance to track the knee of the road-torque versus wheel velocity envelope as a function of time. The only parameters employed are wheel deceleration, wheel velocity and mode time for mode-switching between the several control modes (selective brake pressure attenuation and restoration) employed, while the modes themselves include preselective time-scheduling of the respective brake pressure attenuation and restoration.

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Fullerton, CA, United States of America

George A Watson