International Business Machines Corporation

George A Katopis

Wiren Dale Becker

John Ulrich Knickerbocker

Paul Stephen Andry

Zhaoqing Chen

Bucknell Chapman Webb

Stephen L Buchwalter

Bruce John Chamberlin

Erich Klink

Roland Frech

Thomas-Michael Winkel

Stelios G Tsapepas

Evan G Colgan

Robert K Montoye

Harm Peter Hofstee

Andreas Huber

Chirag Suryakant Patel

Timothy Gerard McNamara

Tin-Chee Lo

Gerard Vincent Kopcsay

Herbert I Stoller

Roger Scott Krabbenhoft

Barry Jay Rubin

Alina Deutsch

Bradley David McCredie

David Allan Webber

Gerald J Fahr

Evan Ezra Davidson

Craig R Selinger

Charles Kyriakos Vakirtzis

Dierk Kaller

Chandrashekhar Ramaswamy

Paul R Turgeon

Christopher W Surovic

Andreas Rebmann

Gerald W Mahoney

Joseph L Braun

A silicon carrier structure for electronic packaging includes a base substrate, a silicon carrier substrate disposed on the base substrate, a memory chip disposed on the silicon carrier substrate, a microprocessor chip disposed on the silicon carrier substrate, an input/output chip disposed on the silicon carrier substrate, and a clocking chip disposed on the silicon carrier substrate.

Silicon carrier structure and method of forming same

An electronic device assembly is provided which includes a substrate, an interposer and an integrated circuit chip. The substrate is fabricated of a first material having a first thermal expansivity, and the interposer and integrated circuit chip are fabricated of a second material having a second thermal expansivity. The second thermal expansivity is different from the first thermal expansivity so that there is a coefficient of thermal expansion mismatch between the substrate and the interposer or chip. The interposer is coupled to the substrate via a first plurality of electrical contacts and an underfill adhesive at least partially surrounding the electrical contacts to bond the interposer to the substrate and thereby reduce strain on the first plurality of electrical contacts. The integrated circuit chip is coupled to the interposer via a second plurality of electrical contacts only, without use of an adhesive surrounding the second plurality of electrical contacts.

Reworkable electronic device assembly and method

A system and method for performing a test for characterizing high frequency operation of PCB boards. More particularly, a system and methodology is provided to implement a time-domain short pulse propagation (SPP) technique on the production line, on large, multi-layer, product-level PCB boards, for large volume testing, by people who are not familiar with advanced, delicate, measurement techniques, who need robust test facilities, and cannot afford the time or expense of other lab-type approaches.

System and method implementing short-pulse propagation technique on production-level boards with incremental accuracy and productivity levels

Signal line conductors passing through vertical vias in an insulative substrate for supporting and interconnecting integrated circuit chips are provided with shielding conductors in adjacent vias that link respective power and ground planes. The shielding conductors' presence in positions around a signal via is made possible through the employment of power plane and ground plane conductive grids that are laid out in rhomboid patterns. The power plane and ground plane grids possess a left-right mirror relation to one another and are displaced to place the rhomboid's corners to avoid overlapping any of the grid lines.

Ceramic substrate grid structure for the creation of virtual coax arrangement

The present invention relates to computer hardware design, and in particular to a printed circuit board (card) comprising wiring dedicated to supply electric board components such as integrated circuits with at least three different reference planes. In particular at locations, where the pins of a card-to-card connector enter the layer structure of the card discontinuities brake the high frequency signal return path of a given signal wiring. In order to close the signal return path around a signal path from card to card including the connector, and thus to limit the signal coupling while concurrently keeping the card design as simple as possible, it is proposed to provide

Circuit on a printed circuit board

The present invention relates to computer hardware design and in particular to a printed circuit board comprising wiring dedicated to supply electric board components such as integrated circuits with at least three different reference planes. In order to provide a printed circuit board having an improved signal return path for basically all relevant signal layers at transitions between card, connector, module and chip while still holding the cross-section structure simple, it is proposed to establish a layer structure wherein a) a split voltage plane is located adjacent to one side of one of said reference planes and comprises conducting portions for all of said at least three different voltage levels in respective plane parts, and b) a signal layer being located adjacent to said reference planes.

Printed circuit board and chip module

A multiple power density packaging structure with two or more semiconductor chips on a common wiring substrate having a common thermal spreader with a planar surface in thermal contact with the non-active surfaces of the chips. The semiconductor chips have different cooling requirements and some of the chips are thinned to insure that the chips requiring the lowest thermal resistance has the thinnest layer of a thermal adhesive or metal or solder interface between the chip and thermal spreader.

Multiple power density chip structure

A method for dynamic bandwidth testing of a link between two computer subsystems useful for determining the amount of data which can be buffered in a transmission line by delay, in which at each end of the line circuit modules are provided to couple the subsystem by a bi-directional multi-bit (BiDi) link, and providing within each said circuit module a built-in circuit and logic for dynamic transmission characterization and test of a said BiDi link between computer subsystems using built-in characterization logic macros, and during a test mode, switching said said built-in circuit and logic to test mode and using the test mode to characterize the link performance, and after the completion of characterization, the switching built-in characterization logic macros back to a normal system mode after programmatically setting timing parameters for the BiDi link to ensure safe operation of data transfer before the BiDi link is switched to system mode.

Method for dynamic bandwidth testing

Switching characteristics of system components are represented and summed so that their effects on the overall system can be observed during the design process. Full simultaneous switching analysis is provided at the earliest levels of design containing minimal level of design data by a method of computing net based simultaneous switching noise levels which supports packages ranging from the smallest chip level to the largest board level. The simultaneous switching activity is computed based on interaction between each driver and each other driver between each component and each other component, with consideration to the spatial inter-relationship net, within a higher level component, to determine each component's drivers effect on itself as well as the coupling effect between drivers on different components. The analysis involves computing simultaneous switching noise by associating a characteristic triangle with each driver application configuration. The characteristic triangle. The height of the triangle, as well as the pitch of the sides of the triangle will be determined by the characteristics of the net. In the early stages of design, a default characteristic triangle is defined for each technology type. A general triangle is also defined for cases where early analysis needs to be performed prior to choosing a technology.

Early high level net based analysis of simultaneous switching

A clamping circuit to reduce self-induced switching noise in a multi-chip module semiconductor structure. A module section interconnects the chips and the chips have a power supply and power leads respectively. An impedance path is defined between each of the chips and the power supply to define a current path for switching noise through the top of the module. A high impedance path is defined for voltages below a predetermined upper limit of the chip supply voltage and a low impedance path is defined by the clamping circuit for the voltage range where noise superimposed on the chip supply voltage occurs.

On-chip Delta-I noise clamping circuit

Growing community of inventors

Poughkeepsie, NY, United States of America

George A Katopis