International Business Machines Corporation

George A Kaplita

Nicholas J Giammarco

Joseph F Shepard

Jeffrey J Brown

Anthony F Scaduto

Alexander D Lopata

Alexander Gimpelson

Stefan Schmitz

Chienfan Yu

Rebecca D Mih

Joyce C Liu

John W Golz

John S Lechaton

Jin J Wu

Len Yuan Tsou

Teresa Jacqueline Wu

Christopher N Collins

Thomas A Hansen

James A Bondur

Senthil K Srinivasan

James C Brighten

Wilson Tong Lee

A method for fabricating a dual gate structure, comprising providing a semiconductor substrate having a first device area and a second device area covered by a gate oxide layer and a polysilicon layer, forming a first hard mask over the polysilicon layer, said first hard mask being a material that is resistant to a first etching, but susceptible to a second etching forming a second hard mask over the first hard mask and the polysilicon layer, said second hard mask being a material that is resistant to a second etching, but susceptible to a first etching, patterning and etching said second hard mask with a first etch to form a gate pattern on a first device area, and patterning and etching said first hard mask with a second etch to transfer gate patterns on the first and second device areas.

Dual mask process for semiconductor devices

A cleaning wafer is used during the vaporization of particulate deposits that were previously deposited on the walls of a plasma chamber. The cleaning wafer includes a first dielectric layer, a conducting layer and a second dielectric layer covering the conducting layer.

Universal cleaning wafer for a plasma chamber

Disclosed is a process for reducing lithographic image size for integrated circuit manufacture. A mask of photosensitive material having an opening of a minimum size dictated by the limits of lithography is formed on a substrate. Reduction in the image size is achieved by establishing sidewalls to the interior vertical surfaces of the opening by depositing a conformal layer, followed by anisotropic etching. The dimension of the opening is reduced by the combined thickness of the two opposite insulator sidewalls. In a specific direct application of the disclosed process, a photomask/stencil having a pattern of openings of a minimum size smaller than possible by lighography, per se, is formed.

Mask using lithographic image size reduction

Disclosed is a process for etching semiconductor materials with a high etch rate against an insulator mask using a novel etchant gas mixture. The mixture consists of a chlorocarbon (e.g., CCl.sub.2 F.sub.2, CCl.sub.4 or CCl.sub.3 F), SF.sub.6, O.sub.2 and an inert gas (e.g. He). The preferred gas mixture contains 2/1 ratio of the chlorocarbon to SF6 and the following composition: 1-4% of SF.sub.6, 3-10% of O.sub.2, 74-93% of He and 3-10% of chlorocarbon. The etch rate of silicon (or silicide) against an oxide mask using this etchant gas mixture under normal etching conditions is high, on the order of 30-40. An impressive feature of the process is shape control of trenches by mere manipulation of the RIE system power.

RIE process for etching silicon isolation trenches and polycides with

Disclosed is a process for reducing lithographic image size for integrated circuit manufacture. A mask of photosensitive material having an opening of a minimum size dictated by the limits of lithography is formed on a substrate. Reduction in the image size is achieved by establishing sidewalls to the interior vertical surfaces of the opening by depositing a conformal layer, followed by anisotropic etching. The dimension of the opening is reduced by the combined thickness of the two opposite insulator sidewalls. In a specific direct application of the disclosed process, a photomask/stencil having a pattern of openings of a minimum size smaller than possible by lithography, per se, is formed.

Lithographic image size reduction

Disclosed is a RIE apparatus wherein the anode (maintained at ground potential) is composed of a three-plate configuration and is disposed in parallel relationship with the cathode plate. The top and middle plates of the anode have small gas pump-out holes and are affixed to the chamber walls below the pump-out port to form a high pressure baffle chamber. A gas ring interposed between the top and middle anode plates permits uniform diffusion of etchant species into the reaction volume. The third plate (plasma potential reduction plate -PPRP) of the anode is flexibly attached to the middle plate and contains a large number of large holes compared to those in the top and middle plates. The minimum size of the holes in the PPRP is twice the plasma dark space to permit the plasma formed in the reaction volume below the PPRP to be sustained thereabove, thereby increasing the ratio of the grounded area to the cathode area to which the plasma is exposed. Consequently, the DC potential is increased and the plasma potential decreased resulting in an enlargement of the wafer load window, elimination of black silicon formation, increasing uniformity of etching across the entire cathode surface and better etch selectivity.

Reactive ion etching apparatus

Growing community of inventors

New Windsor, NY, United States of America

George A Kaplita