Ovonyx Inc.

Intel Corporation

Micron Technology Incorporated

Stmicroelectronics S.r.l.

Ovonyx Memory Technology, LLC

Carlow Innovations LLC

George A Gordon

Tyler A Lowrey

Ilya V Karpov

Ward D Parkinson

Sergey A Kostylev

Gianpaolo Spadini

Semyon D Savransky

James Reed

John M Peters

Stanford R Ovshinsky

Fabio Pellizzer

Agostino Pirovano

Charles C Kuo

Ward M Parkinson

Stephen J Hudgens

Guy Charles Wicker

Charles H Dennison

Disturb from the reset to the set state may be reduced by creating an amorphous phase that is substantially free of crystal nuclei when programming the reset state in a phase change memory. In some embodiments, this can be achieved by using a current or a voltage to program that exceeds the threshold voltage of the phase change memory element, but does not exceed a safe current voltage which would cause a disturb.

Immunity of phase change material to disturb in the amorphous phase

Using a shorter read pulse width may increase read window in some embodiments. This may allow the use of higher voltages with less likelihood of a read disturb where a bit unintentionally changes phase.

Read window in chalcogenide semiconductor memories

A phase change memory cell may be read by driving a current through the cell higher than its threshold current. A voltage derived from the selected column may be utilized to read a selected bit of a phase change memory. The read window or margin may be improved in some embodiments. A refresh cycle may be included at periodic intervals.

Using higher current to read a triggered phase change memory

A phase change memory cell may be formed with a pair of chalcogenide phase change layers that are separated by a breakdown layer. The breakdown layer may be broken down prior to use of the memory so that a conductive breakdown point is defined within the breakdown layer. In some cases, the breakdown point may be well isolated from the surrounding atmosphere, reducing heat losses and decreasing current consumption. In addition, in some cases, the breakdown point may be well isolated from overlying and underlying electrodes, reducing issues related to contamination. The breakdown point may be placed between a pair of chalcogenide layers with the electrodes outbound of the two chalcogenide layers.

Forming phase change memories with a breakdown layer sandwiched by phase change memory material

A memory may be implemented with a stable chalcogenide glass which is defined as a generally amorphous chalcogenide material that does not change to a generally crystalline phase when exposed to 200&#xb0; C. for 30 minutes or less. Different states may be programmed by changing the threshold voltage of the material. The threshold voltage may be changed with pulses of different amplitude and/or different pulse fall times. Reading may be done using a reference level between the threshold voltages of the two different states. A separate access device is generally not needed.

Programming a normally single phase chalcogenide material for use as a memory of FPLA

A method for programming a phase change memory cell is discussed. A phase change memory cell includes a memory element of a phase change material having a first state, in which the phase change material is crystalline and has a minimum resistance level, a second state in which the phase change material is amorphous and has a maximum resistance level, and a plurality of intermediate states, in which the phase change material includes both crystalline regions and amorphous regions and has intermediate resistance levels. According to the method, a plurality of programming pulses are provided to the phase change memory cell; programming energies respectively associated to the programming pulses are lower than a threshold energy which is required to bring the phase change material to the second state.

Multilevel programming of phase change memory cells

Programming a normally single phase chalcogenide material for use as a memory or FPLA

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Sunnyvale, CA, United States of America

George A Gordon