Motorola Corporation

George A Drapac

Stephen H Woltz

Walter L Davis

Mark L Oliboni

Michael J DeLuca

Gary L Pace

Walter J Grandfield

Paul J Godfrey

Keith Edward Jackoski

A driver circuit (100) is utilized to drive a high current load (116) in an electronic device powered by a battery (118) having a terminal voltage which varies in relation to a level of energy being consumed. The driver circuit (100) includes a differential amplifier (110) which is responsive to a predetermined reference voltage and to the terminal voltage for generating a drive control signal which proportionally reduces a current supplied to the high current load (114) when the terminal voltage is substantially equal to and lower than the predetermined reference voltage. A slope control element (112) is coupled to the differential amplifier (110) to control a rate at which the drive control signal reduces proportionally the current supplied to the high current load (116). A load control element (114), coupled to the differential amplifier (100), provides the supply of current to the high current load (116).

Driver circuit providing controllable battery overload protection

In a device having a primary battery 10, a first voltage multiplier 20 is used to power digital electrical circuits 40 from the primary battery, and a second voltage multiplier 100-136 is used to recharge a backup battery 50 from the primary battery. The backup battery is charged to a voltage greater than the voltage generated by the first voltage multiplier. Methods of controlling the second voltage multiplier reduce its interference in measurement of device parameters, and reduce the power consumed from the primary battery.

Backup battery system for a portable electronic device

In a selective call radio paging device, a plurality of alerts are generated in response to the decoding of a message having an address corresponding to the address assigned to the pager. A specific alert envelope waveform is generated and drives an alerting device of a first type (e.g., a transducer). Inverting means is provided to invert the envelope and cause a second alerting device (e.g., visual) to be activated in a manner complementary to the first. Thus, alerting devices are not operated concurrently, and peak loads on a resident power source are avoided.

Paging device with alternating alert outputs

A paging receiver capable of bit synchronizing to one of two data rates. The receiver has a digital phase locked loop integrated onto a single integrated circuit clocked by a single frequency crystal. The paging receiver receives and synchronizes to a POCSAG signal which may be transmitted at either 512 bits per second or 1200 bits per second. The digital phase locked loop bit synchronizes to either data rate using a single crystal frequency of 76.8 kHz. The data rate is selected by a bit in the code paging receiver's code plug. The digital phase locked loop is constructed to have a substantially constant frequency to bandwidth ratio at both data rates.

Bit synchronizer

The pager receiver including a conventional address decoder, an alert envelope waveform generator, and an alert function mapper is disclosed. The pager is individually and uniquely characterized by programming the alert function mapper to govern the generation of assigned alert annunciation patterns by the waveform generator in response to selected decoded pager addresses and associated functions thereof, and to inhibit alert generation by the waveform generator in response to non-selected decoded pager addresses and associated functions thereof. In one embodiment, the alert signal waveform generator is enabled to respond to the alert function mapper only when the pager address is decoded by the decoder.

Programmable multi-address pager receiver and method of characterizing

A battery saving apparatus for supplying power to a selective call communication receiver for enabling the detection of a synchronization codeword in data received in a predetermined signaling format comprises circuits for supplying power to the receiver, and for detecting valid data received during a first portion of the first predetermined time interval. Power is maintained to the receiver for the remainder of the first predetermined time interval when valid data is detected in the first portion. A synchronization codeword detector is included for detecting a synchronization codeword. When valid data is subsequently detected following a second portion of the first predetermined time interval and the synchronization codeword is not detected in the first predetermined time interval, power is maintained to the receiver for a second predetermined time interval to further enable detection of the synchronization codeword.

Battery saving apparatus and method providing optimum synchronization

A pager receiver includes at least one lock-out circuit, an out-of range circuit, and a single timer coupled to the lock-out and out-of range circuits and responsive to timing signals generated by the pager for generating an initiated one of either the lock-out timer interval or out-of range time interval. Each lock-out circuit of the pager receiver corresponds to an address function programmed therein and is activated by the function detect signal generated in response to the initial decoding of the corresponding address function to initiate the generation of the lock-out time interval by the single timer and to inhibit the corresponding alert annunciation from responding to subsequently generated function detect signals corresponding thereto for the duration of the lock-out time interval. The single timer is also initiated to generate the out-of-range time interval at the generation of each sync pulse timing signal by the pager receiver, but only in the absence of an activated lock-out circuit. Accordingly, the single timer is disabled from initiating the generation of the out-of-range time interval for the duration of an initiated lock-out time interval. Still further, the single timer may be reinitiated to generate the lock-out time interval during the generation of a lock-out time interval by an activated lock-out circuit corresponding to an uninhibited alert annunciation.

Pager receiver having a common timer circuit for both sequential

A radio signal receiving apparatus such as a pager with a security circuitry includes operator-controlled switches for providing a plurality of different command signals which are used to actuate the receiving apparatus in a different mode of operation, an interface circuitry with an optional feature circuitry coupled to the receiving circuitry of the apparatus for providing various optional functions such as automatic reset, single/dual function or battery saving functions to the receiving apparatus, and a security circuitry for preventing the receiving apparatus from receiving the incoming signal once tampering of the optional feature security is detected.

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Boca Raton, FL, United States of America

George A Drapac