Infineon Technologies Ag

Siemens Aktiengesellschaft

Infineon Technoloiges Ag

Georg Tempel

Franz Schuler

Ronald Kakoschke

Danny Shum

Laurent Breuil

Dietrich Widmann

Achim Gratz

Ernst-Otto Andersen

Michael Schmidt

Christoph Kutter

Franz Hofmann

Christoph Ludwig

Roman Knoefler

Josef Winnerl

Robert Strenz

Stephan Riedel

Bernhard Knott

Ludger Heiliger

Gerhard Poeppel

Veronika Polei

Elard Stein Von Kamienski

Armin Hanneberg

Robert Wiesner

Rolf-Peter Vollertsen

Stefan Trost

Matthias Ernst

Martin Steinbrück

Roland Haberkern

A method for evaluating a chip manufacturing process is described comprising measuring, for each of a plurality of chips manufactured in a chip manufacturing process, a bit failure rate of the chip, determining a distribution of bit failure rates from the measured bit failure rates; determining a maximum allowed bit failure rate from a given chip failure rate limit, determining a value representing the probability that a chip manufactured in the chip manufacturing process is below the maximum allowed bit failure rate and determining, based on the value, whether the chip manufacturing process is suitable for the chip failure rate limit.

Method and device for evaluating a chip manufacturing process

A chip includes a logic circuit which has a plurality of transistors and is configured to carry out a logical data processing function, the transistors being operated in a first direction when carrying out the data processing function, and a readout circuit which is configured to control the logic circuit in such a manner that the transistors are operated in a second direction opposite the first direction and is configured to determine an identification of the logic circuit on the basis of an output from the logic circuit when operating the transistors in the second direction.

Chip and method for identifying a chip

A semiconductor device and method of making a semiconductor device are disclosed. A semiconductor body, a floating gate poly and a source/drain region are provided. A metal interconnect region with a control gate node is provided that capacitively couples to the floating gate poly.

Semiconductor device and method of making same

Method of making semiconductor device

The invention relates to a semiconductor component with trench isolation and to an associated fabrication method, a trench isolation (STI, TTI) having a deep isolation trench with a covering insulation layer (), a side wall insulation layer () and an electrically conductive filling layer (), which is electrically connected to a predetermined doping region () of the semiconductor substrate in a bottom region of the trench. The use of a trench contact (DTC), which has a deep contact trench with a side wall insulation layer () and an electrically conductive filling layer (), which is likewise electrically connected to the predetermined doping region () of the semiconductor substrate in a bottom region of the contact trench, makes it possible to improve the electrical shielding properties with a reduced area requirement.

Semiconductor component with trench isolation and corresponding production method

A nonvolatile memory element and associated production methods and memory element arrangements are presented. The nonvolatile memory element has a changeover material and a first and second electrically conductive electrode present at the changeover material. To reduce a forming voltage, a first electrode has a field amplifier structure for amplifying a field strength of an electric field generated by a second electrode in a changeover material. The field amplifier structure is a projection of the electrodes which projects into the changeover material. The memory element arrangement has multiple nonvolatile memory elements which are arranged in matrix form and can be addressed via bit lines arranged in column form and word lines arranged in row form.

Nonvolatile memory element and production method thereof and storage memory arrangement

The invention relates to a semiconductor component with trench isolation and to an associated fabrication method, a trench isolation having a deep isolation trench with a covering insulation layer, a side wall insulation layer and an electrically conductive filling layer, which is electrically connected to a predetermined doping region of the semiconductor substrate in a bottom region of the trench. The use of a trench contact, which has a deep contact trench with a side wall insulation layer and an electrically conductive filling layer, which is likewise electrically connected to the predetermined doping region of the semiconductor substrate in a bottom region of the contact trench, makes it possible to improve the electrical shielding properties with a reduced area requirement.

Semiconductor component with trench insulation and corresponding production method

The invention relates to a semiconductor component with stress-absorbing semiconductor layer (SA) and an associated fabrication method, a crystalline stress generator layer (SG) for generating a mechanical stress being formed on a carrier material (). An insulating stress transmission layer (), which transmits the mechanical stress which has been generated to a stress-absorbing semiconductor layer (SA), is formed at the surface of the stress generator layer (SG), with the result that in addition to improved charge carrier mobility, improved electrical properties of the semiconductor component are also obtained.

Semiconductor component with stress-absorbing semiconductor layer

A bit line structure and associated fabrication method are provided for a semiconductor element or circuit arrangement. The bit line structure contains a surface bit line and a buried bit line. The buried bit line is formed in an upper section of a trench and is connected to an associated first doping region via a first connection layer. A first trench filling layer, which is insulated from the buried bit line by a second trench insulating layer, is situated in a lower section of the trench.

Bit line structure and method for the production thereof

The invention relates to a nonvolatile two-transistor semiconductor memory cell and an associated fabrication method, source and drain regions () for a selection transistor (AT) and a memory transistor (ST) being formed in a substrate (). The memory transistor (ST) has a first insulation layer (), a charge storage layer (), a second insulation layer () and a memory transistor control layer (), while the selection transistor (AT) has a first insulation layer (') and a selection transistor control layer (*). By using different materials for the charge storage layer () and the selection transistor control layer (), it is possible to significantly improve the charge retention properties of the memory cell by adapting the substrate doping with electrical properties remaining the same.

Non-volatile two transistor semiconductor memory cell and method for producing the same

The invention relates to a nonvolatile semiconductor memory cell and to an associated fabrication method, a source region (), a drain region () and a channel region lying in between being formed in a substrate (). In order to realize locally delimited memory locations (LB, RB), an electrically non-conductive charge storage layer () situated on a first insulation layer () is divided by an interruption (U), thereby preventing, in particular, a lateral charge transport between the memory locations (LB, RB) and significantly improving the charge retention properties.

Non-volatile two-transistor semiconductor memory cell and method for producing the same

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Dresden, Germany

Georg Tempel