Infineon Technologies Ag

Siemens Aktiengesellschaft

Georg Georgakos

Thomas Zettler

Dirk Hammerschmidt

Bernhard Gstoettenbauer

Rafael Zalman

Veit Kleeberger

Ludwig Rossmeier

Stephan Henzler

Christian Pacha

Doris Schmitt-Landsiedel

Michael Goessel

Jörg Berthold

Bernhard Dobler

Thomas Kern

Thomas Nirschl

Thomas Baumann

Anselme Urlick Tchegho Kamgaing

Alexander Nielsen

Christoph Ludwig

Josef Winnerl

Kazimierz Szczypinski

Wolfgang Pockrandt

Joerg Berthold

Gerhard Nebel

Siegmar Koeppe

Elard Stein Von Kamienski

Martin Bloch

Jakob Kriz

Diether Sommer

Ulrich Kleine

Christoph Kutter

Anton Huber

Egor Sogomonyan

Thomas Niedermeier

Roswitha Deppe

Matthias Schobinger

Thomas Piorek

Kai Huckels

Peter Wawer

J&uuml;rgen Peter

Kai Kasprick

Sascha Siegler

Andreas Liebelt

In some examples, a circuit comprises a function unit configured to perform a circuit function, and one or more in situ monitors configured to measure internal data associated with the circuit. The circuit may further comprise a memory configured to store one or more limit values associated with the one or more in situ monitors, and a lifetime model unit configured to determine whether the circuit has reached an end-of-life threshold based on the measured internal data from the one or more in situ monitors and the limit values.

Circuits and techniques for predicting end of life based on in situ monitors and limit values defined for the in situ monitors

In some examples, a method of operating a circuit is described. The method may include performing a circuit function and estimating a probability of failure of the circuit based on one or more stress origination metrics, one or more stress victim events, and one or more initial state conditions.

Circuits and techniques for predicting failure of circuits based on stress origination metrics and stress victim events

In some examples, this disclosure describes a method of operating a circuit. The method may comprise performing a circuit function under normal operating conditions, wherein performing the circuit function under the normal operating conditions includes performing at least a portion of the circuit functions via a characteristic circuit, performing at least the portion of the circuit function under enhanced stress conditions via a characteristic circuit replica, and predicting a potential future problem with the circuit function under the normal conditions based on an evaluation of operation of the characteristic circuit relative to operation of the characteristic circuit replica.

Differential aging monitor circuits and techniques for assessing aging effects in semiconductor circuits

In some examples, a method of operating a circuit may comprise performing a circuit function under normal conditions, performing the circuit function under aggravated conditions, predicting a potential future problem with the circuit function under the normal conditions based on an output of the circuit function under the aggravated conditions, and outputting a predictive alert based on predicting the potential future problem.

Circuits and techniques for assessing aging effects in semiconductor circuits

In some examples, a circuit may be configured to perform a method that includes performing a circuit function via a circuit function unit of a circuit, receiving sensor data from one or more sensors associated with the circuit function unit, and estimating a remaining life of the circuit based on an accelerated reliability model and the sensor data, wherein the sensor data comprises input to the accelerated reliability model. The circuit itself may include a dedicated circuit unit that estimates the remaining life of the circuit based on an accelerated reliability model and the sensor data, and the circuit may output one or more predictive alerts or predictive faults when the remaining life is below a threshold, which may prompt the system for predictive maintenance on the circuit.

End-of-life prediction for circuits using accelerated reliability models and sensor data

In an embodiment, a storage device includes a multiplicity of data value memory cells and a multiplicity of check value memory cells, where at least one of the multiplicity of data value memory cells is assigned to two of the check value memory cells, and where at least one of the multiplicity of check value memory cells is assigned to two of the data value memory cells, and a correction circuit which is configured to output a corrected data value when reading out a selected data value memory cell of the at least one of the multiplicity of data value memory cells, based on a content of the selected data value memory cell and based on contents of the two check value memory cells assigned to the selected data value memory cell.

Devices and methods for data storage

Methods and apparatuses relating to error-tolerant memories are provided. In one example embodiment, output signals from at least three memory devices are supplied to an error correction device. The error correction device outputs a corrected data value in such a manner that, when the read data values match, this data value is output and, in at least one state in which the data values do not match, a previously output data value is retained.

Error-tolerant memories

Implementations are presented herein that include a test circuit and a reference circuit.

Semiconductor device with a test circuit and a reference circuit

Structures of a circuit are identified. Voltages are propagated to the identified structures. Additionally, internal node voltages for the identified structures are obtained. Asymmetrical operating conditions are identified.

Circuit analyzer systems and methods

One embodiment of the present invention relates to an error tolerant memory circuit having a low hardware overhead that can tolerate both single volatile soft errors and permanent errors. In one embodiment, the method and apparatus comprise a memory circuit having a plurality of memory element pairs, respectively having two memory storage elements configured to store a data unit. One or more parity generation circuits are configured to calculate a first parity bit from data written to the plurality of memory element pairs (e.g., the two memory storage elements) and a second parity bit from data read from one of the two memory storage elements in the plurality of memory element pairs. Based upon the calculated first and second parity bits, the memory circuit chooses to selectively output data from memory storage elements not known to contain an error.

Error tolerant flip-flops

Circuit arrangement with a test circuit and a reference circuit and corresponding method

In accordance with an embodiment, a FinFET device includes: one or more fins, a dummy fin, a gate line, a gate contact landing pad, and a gate contact element. Each of the fins extends in a first direction above a substrate. The dummy fin extends in parallel with the fins in the first direction above the substrate. The gate line extends in a second direction above the substrate, and partially wraps around the fins. The gate contact landing pad is positioned adjacent to or above the dummy fin and electrically coupled to the gate line. The gate contact element is electrically coupled to the gate contact landing pad and is positioned to the top surface thereof.

Contact structure for FinFET device

An integrated circuit includes functional blocks, a power control unit controlling the provision of power to the different functional blocks of the integrated circuit, a detecting unit detecting if a turned off functional block is to be turned on, and a clock signal control unit controlling the provision of the clock signal for the functional blocks. The clock signal control unit interrupts the clock signal for the activated functional blocks of the integrated circuit for a predetermined number of clock cycles. The power control unit provides power to the turned off functional block during the interrupted clock cycles.

Circuit arrangement for activating a circuit block and method for the same

A layout structure is provided with a conducting line extending in a conducting line direction, the conducting line being arranged within a substrate area, a fill element being arranged within the substrate area at a predetermined distance from the conducting line, the fill element having a fill element axis extending perpendicularly to a side of the fill element in a fill element direction, an angle between the conducting line direction and the fill element direction being greater than 0&#xb0; and smaller than 90&#xb0;.

Layout structure having a fill element arranged at an angle to a conducting line

In a method for designing integrated circuits comprising replacement logic components, a plurality of logic cells and a plurality of filler cells which fill interspaces between the logic cells are positioned on a chip area. In this case, some or all of the filler cells represent replacement logic components for the integrated circuit and have been or are interconnected or wired in such a way that they form capacitances in the integrated circuit.

Method for designing integrated circuits comprising replacement logic gates

Growing community of inventors

Fraunberg, Germany

Georg Georgakos