International Business Machines Corporation

Geordie M Braceras

Harold Pilo

Robert E Busch

Kevin A Batson

Gary S Koch

John Atkinson Fifield

John Edward Barth, Jr

Dale E Pontius

Alan L Roberts

Steven Harley Lamphier

William F Pokorny

A design structure embodied in a machine readable medium used in a design process for small signal sensing during a read operation of a static random access memory (SRAM) cell includes coupling a pair of complementary sense amplifier data lines to a corresponding pair of complementary bit lines associated with the SRAM cell, and setting a sense amplifier so as to amplify a signal developed on the sense amplifier data lines, wherein the bit line pair remains coupled to the sense amplifier data lines at the time the sense amplifier is set.

Apparatus and method for small signal sensing in an SRAM cell utilizing PFET access devices

A keeper device design structure for dynamic logic used in integrated circuit designs includes a first keeper path statically coupled to a dynamic data path, the first keeper path configured to prevent false discharge of the dynamic data path during an evaluation thereof, and a second keeper path selectively coupled to the dynamic data path. The second keeper path is configured to maintain the dynamic data path at a nominal precharge level prior to an evaluation thereof, wherein the second keeper path is decoupled from the dynamic data path during the evaluation.

Design structure for implementing dynamic data path with interlocked keeper and restore devices

A design structure for content addressable memory including a first array of memory cells, and a second array of memory cells. A search logic circuit is configured to prevent a discharge of the second array of memory cells when a search of the first array of memory cells finds certain data.

Design structure for content addressable memory

A high-reliability content & addressable memory using a shadow content-addressable memory (CAM) array in parallel with a primary CAM array to increase the reliability of CAM searches. The reliability of CAM searches has been less than desired because of random environmental influences that corrupt data. The shadow CAM is written, read, and searched in parallel with the primary CAM. The search results from the parallel searches are compared and, if identical, are declared valid. If the search results are not equal, corrective action is initiated. The high-reliability content-addressable memory may be used with or without priority encoders.

High reliability content-addressable memory using shadow content-addressable memory

A high-reliability content-addressable memory using a shadow content-addressable memory (CAM) array in parallel with a primary CAM array to increase the reliability of CAM searches. The reliability of CAM searches has been less than desired because of random environmental influences that corrupt data. The shadow CAM is written, read, and searched in parallel with the primary CAM. The search results from the parallel searches are compared and, if identical, are declared valid. If the search results are not equal, corrective action is initiated. The high-reliability content-addressable memory may be used with or without priority encoders.

An on-chip I/O timings measurement circuit that improves measurement accuracy compared to conventional external test methods. This circuit guarantees AC timing specifications that are too small for the measurement capabilities of today's high-frequency memory testers. This system in incorporated into the SRAM via the JTAG interface and a JTAG private instruction. A private instruction refers to an unused instruction from the industry-standard public instruction set. Private instructions are usually reserved for the manufacturer, but may be provided to the user as an enhancement to the standard JTAG instruction set.

On-chip method for measuring access time and data-pin spread

A method to statically balance Silicon-On-Insulator (SOI) parasitic effects is disclosed. Additionally, eight device Static Random Access Memory (SRAM) cells using the method are provided. A balanced output stage that creates a particular set of parasitic effects, as seen by a node connected to the output of the balanced output stage, is provided. If the balanced output stages are used at both outputs of a SRAM cell, the nodes to which the outputs of the balanced output stages are connected will see the same parasitic effects when the transistors in the balanced output stages are off. Thus, the balanced output stages can create the same effect on both the true and complement bitlines of an SOI SRAM, thereby balancing both of these lines and improving access times.

Method to statically balance SOI parasitic effects, and eight device SRAM cells using same

A SRAM module provides programmability of AC timings such that an end user can adjust or &ldquo;tweak&rdquo; the AC timings to maximize system performance. A variable delay circuit is placed in the path between a signal (e.g., data signal or address signal)and the SRAM set-up and hold register which allows the user to shift the setup-and-hold window by selected increments. The delay circuit can either advance or retard the AC timings. A delay program controlling the delay circuit is selected in one of two ways; either by a default AC timing program stored in a ROM device and preset by the manufacturer, or by a private JTAG instruction and AC programming data input by the user through the JTAG state machine provided on the SRAM chip. Once the optimum delay (or advance) is selected to optimize the SRAM to the cache system this user program may be permanently burned into the default ROM such that the optimum timings are used thereafter as the default.

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Essex Junction, VT, United States of America

Geordie M Braceras