Xilinx, Inc.

Other

Geoffrey Zhang

Hongtao Zhang

Zhaoyin D Wu

Kun-Yung Chang

Yu Liao

Yu Xu

Winson Lin

Yohan Usthavia Frans

Patrick Satarzadeh

Christopher J Borrelli

Parag Upadhyaya

Alan C Wong

Yang Liu

Michael O Jenkins

Romi Mayder

Shuo Jiao

Kevin Zheng

Toan Duc Pham

Jinyung Namkoong

Chuen-Huei Chou

Zao Liu

Bowen Li

Hong Sik Ahn

Ivan O Madrigal

Murtuza Z Cutleriwala

Tianyu Fang

Using 'in-situ on-die time-domain reflectometry (TDR)' with data signal paths of integrated circuits, printed circuit boards, and data processing equipment and systems allows testing, verification and troubleshooting of data channel signal path impedance variations including the package, escape routing, socket, board, and cable/connectors provides fast characterization thereof. Operation of “in-situ on-die TDR” uses existing analog-to-digital converter (ADC) and data transmitter (TX) drivers of an integrated circuit to act as a TDR sampling head by performing a user interface-based TDR sampling with a step-waveform generated by an integrated circuit TX driver. Then sampling the step-waveform with the ADC of the integrated circuit using spline interpolation to obtain the over-sampled waveform. Once the sampled step-waveform is obtained, the TDR profile of the sampled data channels may be calculated. Large amounts of impedance variation data may thus be collected during either integrated circuit manufacturer or customer-built data communications channel testing.

Equipment design and testing using in-situ on-die time-domain reflectometry

Apparatus and associated methods relate to an ADC-based digital receiver including a feedforward equalizer (FFE) that has m precursor taps and n postcursor taps to equalize the precursor portion, and to adapt postcursor intersymbol interference (ISI) through a predetermined equalization coefficient selected to counteract the noise boosting effect associated with the precursor equalization. In an illustrative example, the receiver may dynamically balance noise and ISI through adaptively determining a coefficient hpof a first postcursor tap of a first FFE and a coefficient hof a first postcursor tap of a second equalizer adapted to substantially reduce or eliminate additional ISI introduced by the first FFE. The first FFE may optimize ISI removal and noise reduction, for example. One of the coefficients hand hpmay be predetermined, and then the other coefficient may be iteratively adapted to trade off precursor ISI and postcursor ISI to minimize BER.

Digital noise-shaping FFE/DFE for ADC-based wireline links

Apparatus and associated methods relate to providing a machine learning methodology that uses the machine learning's own failure experiences to optimize future solution search and provide self-guided information (e.g., the dependency and independency among various adaptation behavior) to predict a receiver's equalization adaptations. In an illustrative example, a method may include performing a first training on a first neural network model and determining whether all of the equalization parameters are tracked. If not all of the equalization parameters are tracked under the first training, then, a second training on a cascaded model may be performed. The cascaded model may include the first neural network model, and training data of the second training may include successful learning experiences and data of the first neural network model. The prediction accuracy of the trained model may be advantageously kept while having a low demand for training data.

Machine learning based methodology for adaptative equalization

A method relates generally to comparison of a communications system modelled with a behavioral model and implemented with a circuit realization. In this method, operation of the communications system is simulated with the behavioral model on a computing device to obtain a first pulse response. The simulating includes first equalizing first data with a first equalizer of the behavioral model to obtain the first pulse response. The circuit realization is operated to obtain a second pulse response. The operating includes: second equalizing second data corresponding to the first data with a second equalizer of the circuit realization to obtain the second pulse response. The second pulse response from the circuit realization is loaded to memory of the computing device. The first pulse is loaded to the memory of the computing device. The first pulse response and the second pulse response are compared with one another by the computing device.

Method and system for correlation of a behavioral model to a circuit realization for a communications system

A circuit for determining data error spacing in a data transmitter is disclosed. The circuit comprises a counter; encoding logic configured to receive an output of the counter, wherein the encoding circuit enables generating error spacing information; and a storage element configured to receive an output of the encoding logic.

Circuit for and method of determining error spacing in an input signal

Apparatus and associated methods relate to using a high learning rate to speed up the training of a receiver and switching from a high learning rate to a low learning rate for fine tuning based on exponentially weighted moving average convergence. In an illustrative example, a selection circuit may switch the high learning rate to the low learning rate based on a comparison of a moving average difference eto a predetermined stability criteria Tof the receiver. The moving average difference emay include an exponentially weighted moving average of a difference between two consecutive exponentially weighted moving averages of an operation parameter uof the signal communication channel. By using this method, the training time for the receiver may be advantageously reduced.

Adaptive method to reduce training time of receivers

A receiver circuit for receiving data is described. The receiver circuit comprises a phase detector configured to receive an input data signal; a frequency path circuit configured to receive an output of the phase detector; and a false lock detection circuit configured to receive the output of the phase detector and an output of the frequency path circuit; wherein the false lock detection circuit detects a false lock of the receiver circuit to the input data signal based upon an output of the phase detector and provides a frequency offset to the frequency path circuit. A method of receiving data is also described.

Data receiver circuit and method of receiving data

An example method of capturing an error distribution data for a serial channel includes: receiving a signal from the serial channel at a receiver in an integrated circuit (IC), the signal encoding data using pulse amplitude modulation (PAM) scheme having more than two levels; determining a plurality of symbols from the signal, each of the plurality of symbols encoding a plurality of bits; comparing the plurality of symbols with a plurality of expected symbols to detect a plurality of symbol errors; generating the error distribution data by accumulating numbers of the plurality of symbol errors across a plurality of bins based error type; and transmitting the error distribution data from the receiver to a computing system for processing.

Pam multi-level error distribution signature capture

A receiver includes: an automatic gain controller (AGC) configured to receive an analog signal; an analog-to-digital converter (ADC) configured to receive an output from the AGC and to output a digitized signal, wherein a most significant bit of the digitized signal corresponds to a sliced data, and a least significant bit of the digitized signal corresponds to an error signal; and an adaptation unit configured to control the AGC, the ADC, or both the AGC and the ADC, based at least in part on the digitized signal to achieve a desired data digitization and data slicing.

ADC based receiver

An example apparatus includes an input circuit including a first adder and a first multiplier, the first adder configured to level-shift an input signal by an amount and the first multiplier configured to multiply output of the adder by a factor. The apparatus further includes a multi-stage noise shaping (MASH) circuit having an input coupled to the first multiplier. The apparatus further includes an output circuit including a second multiplier and a second adder, the second multiplier configured to multiply output of the MASH circuit by a reciprocal of the factor and the second adder configured to level-shift output of the second multiplier by an inverse of the amount.

Delta-sigma modulator having expanded fractional input range

A clock and data recovery (CDR) circuit includes a phase detector, a digital loop filter, and a lock detector. The phase detector generates a phase detect result signal in response to phase detection of a plurality of samples. The plurality of samples are generated by sampling a received signal based on a sampling clock a sampling clock provided by a phase interpolator. The digital loop filter includes a phase path and a frequency path for providing a phase path correction signal and a frequency path correction signal based on the phase detect result signal respectively. A phase interpolator code generator generates a phase interpolator code for controlling the phase interpolator based on the phase path correction signal and frequency path correction signal. The lock detector generates a lock condition signal based on the frequency path correction signal, the lock condition signal indicating a lock condition of the CDR circuit.

Systems and methods for clock and data recovery

An example clock and data recovery (CDR) circuit includes a phase interpolator, a fractional-N phase locked loop (PLL) configured to supply a clock signal to the phase interpolator, and a phase detector configured to generate a phase detect result signal in response to phase detection of data samples and crossing samples of a received signal, the data samples and the crossing samples being generated based on a data phase and a crossing phase, respectively, or a sampling clock supplied by a phase interpolator. The CDR circuit further includes a digital loop filter configured to generate a phase interpolator code for controlling the phase interpolator, the digital loop filter including a phase path and a frequency path. The CDR circuit further includes a control circuit configured to control the digital loop filter to disconnect the frequency path from the phase path and to connect the frequency path to a control input of the fractional-N PLL.

Clock and data recovery circuit having tunable fractional-N phase locked loop

A clock and data recovery (CDR) circuit includes a phase detector, a frequency accumulator, and a sequencer circuit. The phase detector generates a phase detect result signal in response to phase detection of a plurality of samples, which are generated by sampling a first data signal from a receiver using a sampling clock. The frequency accumulator accumulates, using a frequency register, frequency offset information from the phase detect result signal to generate an accumulated total. The frequency offset information is associated with a frequency difference between a first reference clock of the receiver and a second reference clock associated with the first data signal. The accumulated total is stored in the frequency register and provided from the frequency register for updating the sampling clock. The sequencer circuit is configured to perform a reset operation to reset the accumulated total in the frequency register based on a sequence of sequence elements.

In an example, an apparatus for detecting signal loss on a serial communication channel coupled to a receiver includes an input, a detector, and an output circuit. The input is configured to receive decisions generated by sampling the serial communication channel using multiplexed decision paths in a decision feedback equalizer (DFE). The detector is coupled to the input and configured to monitor the decisions for at least one pattern generated by the multiplexed decision paths in response to absence of a serial data signal on the serial communication channel. The output circuit is coupled to the detector and configured to assert loss-of-signal in response detection of the at least one pattern by the detector.

Signal loss detector

An example method of performing an eye-scan in a receiver includes: generating digital samples from an analog signal input to the receiver based on a sampling clock, the sampling clock phase-shifted with respect to a reference clock based on a phase interpolator (PI) code; equalizing the digital samples based on first equalization parameters of a plurality of equalization parameters of the receiver; adapting the plurality of equalization parameters and performing clock recovery based on the digital samples to generate the PI code; and performing a plurality of cycles of locking the plurality of equalization parameters, suspending phase detection in the clock recovery, offsetting the PI code, collecting an output of the receiver, resuming the phase detection in the clock recovery, and unlocking the equalization parameters to perform the eye scan.

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San Jose, CA, United States of America

Geoffrey Zhang