Arm Limited

University of Michigan

Arm IP Limited

Geoffrey Wyman Blake

Ali Ghassan Saidi

Stuart David Biles

Trevor N Mudge

Hugo John Martin Vincent

Matthew Lucien Evans

Andreas Lars Sandberg

Prakash Shyamlal Ramrakhyani

Amyas Edward Wykes Phillips

Richard William Earnshaw

Pavel Shamis

Robert Gwilym Dimond

Mitchell Bryan Hayenga

Anirruddha Nagendran Udipi

Peter Guy Middleton

According to the present techniques there is provided a data processing device, for applying to packaging, the device having a flexible substrate, the flexible substrate comprising: storage circuitry to store device data therein; processing circuitry to process the device data; and communication circuitry to communicate with a remote resource to transmit the device data thereto; sensor circuitry to generate sensed device data, and wherein the device is configured to store the sensed device data in the storage circuitry, process the sensed device data and/or transmit the sensed device data to a remote resource.

Device for applying to packaging

Address translation circuitry performs virtual-to-physical address translations using a page table hierarchy of page table entries, wherein a translation between a virtual address and a physical address is defined in a last level page table entry of the page table hierarchy. The address translation circuitry is responsive to receipt of the virtual address to perform a translation determination with reference to the page table hierarchy, wherein an intermediate level page table entry of the page table hierarchy stores an intermediate level pointer to the last level page table entry. The translation determination comprises: calculating a higher level pointer to the intermediate level page table entry by applying a first predetermined function to the virtual address, calculating the intermediate level pointer by applying a second predetermined function to the virtual address, and initiating a memory access to retrieve in parallel the intermediate level pointer from the intermediate level page table entry and the translation from the last level page table entry.

Parallel page table entry access when performing address translations

An apparatus has a monitoring data store for storing monitoring data indicating regions of a memory address space to be monitored for changes, which can include at least two non-contiguous regions. Processing circuitry updates the monitoring data in response to an update monitor instruction. Monitoring circuitry monitors accesses to the memory system and provides a notification to the processing circuitry when data associated with one of the monitored regions has changed. This improves performance and energy efficiency by reducing the overhead of polling changes to multiple regions.

Memory access monitoring

A data processing systemincludes a translation lookaside bufferstoring mapping data entriesindicative of virtual-to-physical address mappings for different regions of physical addresses. A hint generatorcoupled to the translation lookaside buffergenerates hint data in dependence upon the storage of mapping data entries within the translation lookaside buffer. The hint generatortracks the loading of mapping data entries and the eviction of mapping data entries from the translation lookaside buffer. The hint data is supplied to a memory controllerwhich controls how data corresponding to respective different regions of physical addresses is stored within a heterogeneous memory system, e.g. the power state of different portions of the memories storing different regions, which type of memory is used to store different regions.

Managing memory based on hint data generated from mapping data entries

A data processing system utilizing a descriptor ring to facilitate communication between one or more general purpose processors and one or more devices employs a system memory management unit for managing access by the devices to a main memory. The system memory management unit uses address translation data for translating memory addresses generated by the devices into addresses supplied to the main memory. Prefetching circuitry within the system memory management unit serves to detect pointers read from the descriptor ring and to prefetch address translation data into the translation lookaside buffer of the system memory management unit.

Descriptor ring management

A hardware transactional memoryis provided within a multiprocessorsystem with coherency control and hardware transaction memory control circuitrythat serves to at least partially manage the scheduling of processing transactions in dependence upon conflict data. The conflict data characterizes previously encountered conflicts between processing transactions. The scheduling is performed such that a candidate processing transaction will not be scheduled if the conflict data indicates that one of the already running processing transactions has previously conflicted with the candidate processing transaction.

Contention management for a hardware transactional memory

Growing community of inventors

Austin, TX, United States of America

Geoffrey Wyman Blake