International Business Machines Corporation

Geoffrey Wang

Michael J Lee

Michael Richard Ouellette

Michael H Wood

Saiful Islam

Abraham Mathews

Terry Cain Coughlin, Jr

Tuhin Mahmud

Kevin Duc Tran

Eric Lee Carter

Moon Ho Lee

Aspects of the invention include decoding a base address and an offset to generate a first potential memory address and a second potential memory address. A first cell data associated with the first potential memory address of a first partitioned array and a second cell data associated with a second partitioned array are evaluated. Carry-out bit information is received from a summing operation of the base address and the offset, the operating being performed in parallel to the decoding. The carry-out bit information is used to select either the first cell data or the second cell data.

Sum address memory decoded dual-read select register file

Aspects of the invention include obtaining one or more feature values that define an architecture design of a memory array and implementing a machine learning model to obtain a predicted power, performance, and area (PPA) of the memory array based on the one or more features. The predicted PPA output by the machine leaning model is assessed based on predefined PPA goals. A design of an integrated circuit that includes the memory array is finalized and fabricated based on the predicted PPA meeting the predefined PPA goals.

Integrated circuit development using machine learning-based prediction of power, performance, and area

Embodiments herein describe a SRAM that selectively flips received chunks of data from a high power state to a low power state before storing the chunks of data. The SRAM generates a flip bit for each of the data chunks stored in memory. The state of the flip bit varies depending on whether the corresponding data chunk was flipped before being stored in the SRAM. In one embodiment, the SRAM flips the bits in a data chunk before storing the bits only if all the bits are in the high power state. If so, the SRAM sets the flip bit for the data chunk to a first state and changes all the bits to the low power state before storing the data chunk. If not, the SRAM sets the flip bit to a second state and stores the data chunk without changing the states of the bits.

Reducing SRAM power using strategic data pattern storage

A method of, and a circuit for, impedance control. The method comprises the steps of providing an input/output cell having a controllable input/output impedance, providing a reference cell including a node having a variable voltage, and comparing the voltage of the node to a reference voltage. The voltage of the node is adjusted during a defined period and according to a defined procedure, and during that defined period, a digital signal is generated. That digital signal is transmitted to the input/output cell to adjust the input/output impedance. Preferably, the circuit is embodied as a digital controller designed as a synthesized core or macro. The advantage of this implementation is that it never has to be redesigned in future technologies. The digital controller may be carried over to future technologies in the form of VHDL code, which is pure logic and independent of technology.

ASIC architecture for active-compensation of a programmable impedance I/O

A multi-port electronic memory has a write through capability. Control features for enabling a write through path to an output and subsequently disabling without causing data errors due to design and technology variations are provided. Control features are especially beneficial for use with compilable SRAM books.

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Endicott, NY, United States of America

Geoffrey Wang