Advanced Micro Devices Corporation

Intel Corporation

Globalfoundries Inc.

Geoffrey S Strongin

Rodney W Schmidt

Brian C Barnes

Dale E Gulick

Michael R Tucker

Yi Liu

Mark Douglas Hummel

Andrew William Lueck

David S Christie

Kevin John McGrath

David W Smith

Terry Lynn Cole

Mitchell K Alsup

Qadeer Ahmad Qureshi

Michael Haertel

Michael Barclay

William Alexander Hughes

Larry David Hewitt

Ned M Smith

Vedvyas Shanbhogue

James B Keller

David W Grawrock

Howard C Herbert

Willard M Wiseman

Jason Martin

Scott H Robinson

Garth D Hillman

Ralf Findeisen

David Bar-On

Gary H Simpson

Andrew R Rawson

David M Durham

Siddhartha Chhabra

Michael Lemay

Frederick Daniel Weber

Keith L Shippy

Karanvir Ken S Grewal

Balaji Vembu

Gilbert A Neiger

Ravi L Sahita

Uday R Savagaonkar

Prashant Dewan

Carlos V Rozas

Francis X Mckeen

Tobias Max Kohlenberg

Karanvir S Grewal

Scott R Janus

Ittai Anati

Uttam K Sengupta

Alexander Klaiber

Michael A Goldsmith

Shlomo Raikin

Gideon Gerzon

Ronald Perez

Hisham Shafi

Xiaozhu Kang

Alex Berenzon

Ramya Jayaram Masti

Mark E Scott-Nash

Gur Hildesheim

Iris Sorani

Paul S Schmitz

Stephen J Allen

Norm M Hack

Alpha T Narendra Trivedi

Paul Erb

A host Virtual Machine Monitor (VMM) operates 'blindly,' without the host VMM having the ability to access data within a guest virtual machine (VM) or the ability to access directly control structures that control execution flow of the guest VM. Guest VMs execute within a protected region of memory (called a key domain) that even the host VMM cannot access. Virtualization data structures that pertain to the execution state (e.g., a Virtual Machine Control Structure (VMCS)) and memory mappings (e.g., Extended Page Tables (EPTs)) of the guest VM are also located in the protected memory region and are also encrypted with the key domain key. The host VMM and other guest VMs, which do not possess the key domain key for other key domains, cannot directly modify these control structures nor access the protected memory region. The host VMM, however, using VMPageIn and VMPageOut instructions, can build virtual machines in key domains and page VM pages in and out of key domains.

Secure public cloud using extended paging and memory integrity

A method includes receiving, by a processor from a virtual machine (VM) executed by the processor, an indication that a proper subset of a plurality of virtual memory pages of the VM are secure memory pages. The method further includes, responsive to determining the VM is attempting to access a first memory page, determining whether the proper subset comprises the first memory page. The method further includes, responsive to determining the proper subset comprises the first memory page: using first attributes specified by the VM for the first memory page; and ignoring second attributes specified by a virtual machine monitor (VMM) for the first memory page. The VMM is executed by the processor to manage the VM.

Split-control of page attributes between virtual machines and a virtual machine monitor

Sensor data may be filtered in a secure environment. The filtering may limit distribution of the sensor data. Filtering may modify the sensor data, for example, to prevent identification of a person depicted in a captured image or to prevent acquiring a user's precise location. Filtering may also add or require other data use controls to access the data. Attestation that a filter policy is being applied and working properly or not may be provided as well.

Verified sensor data processing

Technologies for sensor privacy on a computing device include receiving, by a sensor controller of the computing device, sensor data from a sensor of the computing device; determining a sensor mode for the sensor; and sending privacy data in place of the sensor data in response to a determination that the sensor mode for the sensor is set to a private mode. The technologies may also include receiving, by a security engine of the computing device, a sensor mode change command from a user of the computing device via a trusted input/output path of the computing device; and sending a mode command to the sensor controller to set the sensor mode of the sensor based on the sensor mode change command, wherein the sending the mode command comprises sending the mode command over a private bus established between the security engine and the sensor controller. Other embodiments are described herein.

Sensor privacy mode

A processor of an aspect includes operation mode check logic to determine whether to allow an attempted access to an operation mode and access type protected memory based on an operation mode that is to indicate whether the attempted access is by an on-die processor logic. Access type check logic is to determine whether to allow the attempted access to the operation mode and access type protected memory based on an access type of the attempted access to the operation mode and access type protected memory. Protection logic is coupled with the operation mode check logic and is coupled with the access type check logic. The protection logic is to deny the attempted access to the operation mode and access type protected memory if at least one of the operation mode check logic and the access type check logic determines not to allow the attempted access.

Access type protection of memory reserved for use by processor logic

Methods, apparatuses and storage medium associated with providing enhanced privacy during usage of computer vision are disclosed. In embodiments, an apparatus may include one or more privacy indicators to indicate one or more privacy conditions of the apparatus in association with provision of computer vision on the apparatus. The apparatus may further include a privacy engine coupled with the one or more privacy indicators, and configured to pre-process images from an image source of the apparatus associated with the provision of computer vision to the apparatus, to increase privacy for a user of the apparatus, and to control the one or more privacy indicators. In embodiments, the apparatus may include means for blanking out one or more pixels with depth values identified as greater than a threshold. Other embodiments may be described and claimed.

Enhanced privacy for provision of computer vision

In accordance with some embodiments, a protected execution environment may be defined for a graphics processing unit. This framework not only protects the workloads from malware running on the graphics processing unit but also protects those workloads from malware running on the central processing unit. In addition, the trust framework may facilitate proof of secure execution by measuring the code and data structures used to execute the workload. If a part of the trusted computing base of this framework or protected execution environment is compromised, that part can be patched remotely and the patching can be proven remotely throughout attestation in some embodiments.

Secure environment for graphics processing units

In one embodiment, a processor can enforce a blacklist and validate, according to a multi-phase lockstep integrity protocol, a device coupled to the processor. Such enforcement may prevent the device from accessing one or more resources of a system prior to the validation. The blacklist may include a list of devices that have not been validated according to the multi-phase lockstep integrity protocol. Other embodiments are described and claimed.

Providing a multi-phase lockstep integrity reporting mechanism

In one embodiment, a processor comprises a programmable map and a circuit. The programmable map is configured to store data that identifies at least one instruction for which an architectural modification of an instruction set architecture implemented by the processor has been defined, wherein the processor does not implement the modification. The circuitry is configured to detect the instruction or its memory operands and cause a transition to Known Good Code (KGC), wherein the KGC is protected from unauthorized modification and is provided from an authenticated entity. The KGC comprises code that, when executed, emulates the modification. In another embodiment, an integrated circuit comprises at least one processor core; at least one other circuit; and a KGC source configured to supply KGC to the processor core for execution. The KGC comprises interface code for the other circuit whereby an application executing on the processor core interfaces to the other circuit through the KGC.

Known good code for on-chip device management

Growing community of inventors

Austin, TX, United States of America

Geoffrey S Strongin